Merge pull request #674 from Silabs-ArjanB/ArjanB_priondi

Clarified relative priority of NMIs, interrupts, debug, exceptions

Author: silabs-oysteink

docs/user_manual/source/debug.rst

@@ -19,7 +19,6 @@ The following list shows the simplified overview of events that occur in the cor
  #. Points the PC to the location determined by the input port ``dm_haltaddr_i``
  #. Begins executing debug control code
 
-
 Debug Mode can be entered by one of the following conditions:
 
  - External debug event using the ``debug_req_i`` signal
@@ -50,6 +49,8 @@ A trigger match will cause debug entry if ``tdata1.ACTION`` is 1.
 
 The |corev| will not support the optional debug features 10, 11, & 12 listed in Section 4.1 of [RISC-V-DEBUG]_. Specifically, a control transfer instruction's destination location being in or out of the Program Buffer and instructions depending on PC value shall **not** cause an illegal instruction.
 
+|corev| prioritizes debug mode entry below NMIs, but above regular interrupts and synchronous exceptions.
+
 Interface
 ---------
 

docs/user_manual/source/exceptions_interrupts.rst

@@ -68,6 +68,8 @@ Non Maskable Interrupts (NMIs) update ``mepc``, ``mcause`` and ``mstatus`` simil
    ``mstatus`` in response to NMIs, see https://github.com/riscv/riscv-isa-manual/issues/756. If this behavior is
    specified at a future date, then we will reconsider our implementation.
 
+NMIs have higher priority than other interrupts for both the basic interrupt architecture and the CLIC interrupt architecture.
+
 If ``SMCLIC`` == 0, then the NMI vector location is as follows:
 
 * Upon an NMI in non-vectored basic mode the core jumps to **mtvec[31:7]**, 5'h0, 2'b00} (i.e. index 0).
@@ -296,6 +298,8 @@ Although the [RISC-V-SMCLIC]_ specification supports up to 4096 interrupts, |cor
 maximum number of supported CLIC interrupts is equal to ``2^SMCLIC_ID_WIDTH``, which can range from 2 to 1024. The ``SMCLIC_ID_WIDTH`` parameter
 also impacts the alignment requirement for the trap vector table, see :ref:`csr-mtvt`.
 
+Interrupt prioritization is mostly performed in the part of CLIC that is external to the core, with the exception that |corev| prioritizes all NMIs above interrupts received via ``clic_irq_i``.
+
 Nested Interrupt Handling
 ~~~~~~~~~~~~~~~~~~~~~~~~~
 |corev| offers hardware support for nested interrupt handling when ``SMCLIC`` == 1.