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Merge pull request #439 from Silabs-ArjanB/ArjanB_docm
Fixing mtvec and mtvt alignment requirements. Better links for spec v…
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‎docs/user_manual/source/control_status_registers.rst

Lines changed: 30 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -446,7 +446,7 @@ Machine ISA (``misa``)
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CSR Address: 0x301
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449-
Reset Value: defined (based on ``A_EXT``, ``M_EXT``, ``X_EXT``, ``X_MISA``)
449+
Reset Value: defined (based on ``RV32``, ``A_EXT``, ``M_EXT``, ``X_EXT``, ``X_MISA``)
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Detailed:
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@@ -599,18 +599,17 @@ Detailed:
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+---------+------------------+---------------------------------------------------------------------------------------------------------------+
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| Bit # | R/W | Description |
601601
+=========+==================+===============================================================================================================+
602-
| 31:12 | RW | **BASE[31:12]**: Trap-handler base address, always aligned to 4096 bytes. |
602+
| 31:7 | RW | **BASE[31:7]**: Trap-handler base address, always aligned to 128 bytes. |
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+---------+------------------+---------------------------------------------------------------------------------------------------------------+
604-
| 11:2 | WARL (0x0) | **BASE[11:2]**: Trap-handler base address, always aligned to 4096 bytes. ``mtvec[11:2]`` is hardwired to 0x0. |
604+
| 6:2 | WARL (0x0) | **BASE[6:2]**: Trap-handler base address, always aligned to 128 bytes. ``mtvec[6:2]`` is hardwired to 0x0. |
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+---------+------------------+---------------------------------------------------------------------------------------------------------------+
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| 1:0 | WARL (0x0*, 0x1) | **MODE[0]**: Interrupt handling mode. 0x0 = non-vectored basic mode, 0x1 = vectored basic mode. |
607607
+---------+------------------+---------------------------------------------------------------------------------------------------------------+
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609-
The initial value of ``mtvec`` is equal to {**mtvec_addr_i[31:12]**, 10'b0, 2'b01}.
609+
The initial value of ``mtvec`` is equal to {**mtvec_addr_i[31:7]**, 5'b0, 2'b01}.
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When an exception or an interrupt is encountered, the core jumps to the corresponding
612-
handler using the content of the ``mtvec[31:8]`` as base address. Only
613-
8-byte aligned addresses are allowed. Both direct mode and vectored mode
612+
handler using the content of the ``mtvec[31:7]`` as base address. Both direct mode and vectored mode
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are supported.
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.. _csr-mtvec-smclic:
@@ -627,14 +626,14 @@ Detailed:
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+---------+------------------+---------------------------------------------------------------------------------------------------------------+
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| Bit # | R/W | Description |
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+=========+==================+===============================================================================================================+
630-
| 31:12 | RW | **BASE[31:12]**: Trap-handler base address, always aligned to 4096 bytes. |
629+
| 31:7 | RW | **BASE[31:7]**: Trap-handler base address, always aligned to 128 bytes. |
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+---------+------------------+---------------------------------------------------------------------------------------------------------------+
632-
| 11:2 | WARL (0x0) | **BASE[11:2]**: Trap-handler base address, always aligned to 4096 bytes. ``mtvec[11:2]`` is hardwired to 0x0. |
631+
| 6:2 | WARL (0x0) | **BASE[6:2]**: Trap-handler base address, always aligned to 128 bytes. ``mtvec[6:2]`` is hardwired to 0x0. |
633632
+---------+------------------+---------------------------------------------------------------------------------------------------------------+
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| 1:0 | WARL (0x3) | **MODE**: Interrupt handling mode. Always CLIC mode. |
635634
+---------+------------------+---------------------------------------------------------------------------------------------------------------+
636635

637-
The initial value of ``mtvec`` is equal to {**mtvec_addr_i[31:12]**, 10'b0, 2'b11}.
636+
The initial value of ``mtvec`` is equal to {**mtvec_addr_i[31:7]**, 5'b0, 2'b11}.
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639638
.. _csr-mtvt:
640639

@@ -652,13 +651,18 @@ Detailed:
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+-------------+------------+-----------------------------------------------------------------------+
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| Bit # | R/W | Description |
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+=============+============+=======================================================================+
655-
| 31:6 | RW | **BASE**: Trap-handler vector table base address, 64 byte aligned. |
654+
| 31:8 | WARL | **BASE[31:8]**: Trap-handler vector table base address. |
655+
| | | See note below for alignment restrictions. |
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+-------------+------------+-----------------------------------------------------------------------+
657-
| 5:0 | R (0x0) | Reserved. Hardwired to 0. |
657+
| 7:6 | WARL (0x0) | **BASE[7:6]**: Trap-handler vector table base address. |
658+
+-------------+------------+-----------------------------------------------------------------------+
659+
| 5:0 | R (0x0) | Reserved. Hardwired to 0. |
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+-------------+------------+-----------------------------------------------------------------------+
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660-
The ``mtvt`` CSR holds the base address of the trap vector table, aligned on a 64-byte or greater
661-
power-of-two boundary.
662+
.. note::
663+
The ``mtvt`` CSR holds the base address of the trap vector table, aligned on a ``2^(2+SMCLIC_ID_WIDTH)`` bytes or greater
664+
power-of-two boundary. For example if ``SMCLIC_ID_WIDTH`` = 8, then 256 CLIC interrupts are supported and the trap vector table
665+
is aligned to 1024 bytes, and therefore **BASE[9:8]** will be WARL (0x0).
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Machine Status (``mstatush``)
664668
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -756,11 +760,10 @@ Machine Counter-Inhibit Register (``mcountinhibit``)
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CSR Address: 0x320
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759-
Reset Value: 0x0000_000D
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Reset Value: Defined
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761-
The performance counter inhibit control register. The default value is to inihibit counters out of reset.
762-
The bit returns a read value of 0 for non implemented counters. This reset value
763-
shows the result using the default number of performance counters to be 1.
765+
The performance counter inhibit control register. The default value is to inihibit all implemented counters out of reset.
766+
The bit returns a read value of 0 for non implemented counters.
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Detailed:
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@@ -845,14 +848,14 @@ Reset Value: 0x0000_0000
845848
+=============+============+==================================================================================+
846849
| 31 | RW | **INTERRUPT:** This bit is set when the exception was triggered by an interrupt. |
847850
+-------------+------------+----------------------------------------------------------------------------------+
848-
| 30:10 | WLRL (0x0) | **EXCCODE[30:10]**. Hardwired to 0. |
851+
| 30:11 | WLRL (0x0) | **EXCCODE[30:11]**. Hardwired to 0. |
849852
+-------------+------------+----------------------------------------------------------------------------------+
850-
| 9:0 | WLRL | **EXCCODE[30:10]** (See note below) |
853+
| 10:0 | WLRL | **EXCCODE[10:0]**. See note below. |
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+-------------+------------+----------------------------------------------------------------------------------+
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.. note::
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855-
Software accesses to `mcause[7:0]` must be sensitive to the WLRL field specification of this CSR. For example,
858+
Software accesses to `mcause[10:0]` must be sensitive to the WLRL field specification of this CSR. For example,
856859
when `mcause[31]` is set, writing 0x1 to `mcause[1]` (Supervisor software interrupt) will result in UNDEFINED behavior.
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Machine Cause (``mcause``) - ``SMCLIC`` == 1
@@ -880,11 +883,16 @@ Reset Value: 0x0000_0000
880883
+-------------+------------+----------------------------------------------------------------------------------+
881884
| 15:12 | WARL (0x0) | Reserved. Hardwired to 0. |
882885
+-------------+------------+----------------------------------------------------------------------------------+
883-
| 11:10 | WLRL (0x0) | **EXCCODE[11:10]** |
886+
| 11 | WLRL (0x0) | **EXCCODE[11]** |
884887
+-------------+------------+----------------------------------------------------------------------------------+
885-
| 9:0 | WLRL | **EXCCODE[9:0]** |
888+
| 10:0 | WLRL | **EXCCODE[10:0]** |
886889
+-------------+------------+----------------------------------------------------------------------------------+
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891+
.. note::
892+
893+
``mcause.MPP`` and ``mstatus.MPP`` mirror each other. ``mcause.MPIE`` and ``mstatus.MPIE`` mirror each other. Reading or writing the
894+
fields ``MPP``/``MPIE`` in ``mcause`` is equivalent to reading or writing the homonymous field in ``mstatus``.
895+
888896
Machine Trap Value (``mtval``)
889897
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
890898

‎docs/user_manual/source/exceptions_interrupts.rst

Lines changed: 7 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -62,8 +62,8 @@ If multiple interrupts are pending, they are handled in the fixed priority order
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The highest priority is given to the interrupt with the highest ID, except for the Machine Timer Interrupt, which has the lowest priority. So from high to low priority the interrupts are
6363
ordered as follows:
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65-
* ``store bus fault NMI (1021)``
66-
* ``load bus fault NMI (1020)``
65+
* ``store bus fault NMI (1025)``
66+
* ``load bus fault NMI (1024)``
6767
* ``irq_i[31]``
6868
* ``irq_i[30]``
6969
* ...
@@ -90,9 +90,9 @@ In Debug Mode, all interrupts are ignored independent of ``mstatus.MIE`` and the
9090
+----------------+----------------+-------------------------------------------------+-----------------------------------------------------------------+
9191
| 1 | 31-16 | Machine Fast Interrupts | ``irq_i[31]``-``irq_i[16]`` |
9292
+----------------+----------------+-------------------------------------------------+-----------------------------------------------------------------+
93-
| 1 | 1020 | Load bus fault NMI (imprecise) | ``data_err_i`` = 1 and ``data_rvalid_i`` = 1 for load |
93+
| 1 | 1024 | Load bus fault NMI (imprecise) | ``data_err_i`` = 1 and ``data_rvalid_i`` = 1 for load |
9494
+----------------+----------------+-------------------------------------------------+-----------------------------------------------------------------+
95-
| 1 | 1021 | Store bus fault NMI (imprecise) | ``data_err_i`` = 1 and ``data_rvalid_i`` = 1 for store |
95+
| 1 | 1025 | Store bus fault NMI (imprecise) | ``data_err_i`` = 1 and ``data_rvalid_i`` = 1 for store |
9696
+----------------+----------------+-------------------------------------------------+-----------------------------------------------------------------+
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.. note::
@@ -109,7 +109,9 @@ CLIC interrupt handling mode can be used and the ``irq_i[31:0]`` pins are ignore
109109
Interrupts - ``SMCLIC`` == 1
110110
----------------------------
111111

112-
Although the [RISC-V-SMCLIC] specification supports up to 4096 interrupts, |corev| itself is limited to supporting 1024 interrupts (of which interrupts 1020-1023 are reserved for NMIs).
112+
Although the [RISC-V-SMCLIC]_ specification supports up to 4096 interrupts, |corev| itself supports at most 1024 interrupts. The
113+
maximum number of supported CLIC interrupts is equal to ``2^SMCLIC_ID_WIDTH``, which can range from 64 to 1024. The ``SMCLIC_ID_WIDTH`` parameter
114+
also dictates the minimum alignment requirement for the trap vector table to ``2^(2+SMCLIC_ID_WIDTH)`` byte boundaries, see :ref:`csr-mtvt`.
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114116
Non Maskable Interrupts
115117
-----------------------

‎docs/user_manual/source/integration.rst

Lines changed: 10 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -30,7 +30,8 @@ Instantiation Template
3030
.NUM_MHPMCOUNTERS ( 1 ),
3131
.PMA_NUM_REGIONS ( 1 ),
3232
.PMA_CFG ( PMA_CFG[] ),
33-
.SMCLIC ( 0 )
33+
.SMCLIC ( 0 ),
34+
.SMCLIC_ID_WIDTH ( 0 )
3435
) u_core (
3536
// Clock and reset
3637
.clk_i (),
@@ -174,6 +175,11 @@ Parameters
174175
+------------------------------+----------------+---------------+--------------------------------------------------------------------+
175176
| ``SMCLIC`` | int (0..1 ) | 0 | Is Smclic supported? |
176177
+------------------------------+----------------+---------------+--------------------------------------------------------------------+
178+
| ``SMCLIC_ID_WIDTH`` | int (6..10 ) | 6 | Width of ``clic_irq_id_i`` and ``clic_irq_id_o``. The maximum |
179+
| | | | number of supported interrupts in CLIC mode is |
180+
| | | | ``2^SMCLIC_ID_WIDTH``. Trap vector table alignment is restricted |
181+
| | | | to at least ``2^(2+SMCLIC_ID_WIDTH)``, see :ref:`csr-mtvt`. |
182+
+------------------------------+----------------+---------------+--------------------------------------------------------------------+
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179185
Interfaces
@@ -199,9 +205,9 @@ Interfaces
199205
| | | | core via ``fetch_enable_i`` |
200206
+-------------------------+-------------------------+-----+--------------------------------------------+
201207
| ``mtvec_addr_i`` | 32 | in | ``mtvec`` address. Initial value for the |
202-
| | | | address part of :ref:`csr-mtvec`. |
203-
| | | | Must be 4096-byte aligned |
204-
| | | | (i.e. ``mtvec_addr_i[11:0]`` = 0). |
208+
| | | | address part of :ref:`csr-mtvec `. |
209+
| | | | Must be 128-byte aligned |
210+
| | | | (i.e. ``mtvec_addr_i[6:0]`` = 0). |
205211
| | | | Do not change after enabling core |
206212
| | | | via ``fetch_enable_i`` |
207213
+-------------------------+-------------------------+-----+--------------------------------------------+

‎docs/user_manual/source/intro.rst

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -39,11 +39,11 @@ It follows these specifications:
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.. [RISC-V-PRIV] RISC-V Instruction Set Manual, Volume II: Privileged Architecture, Document Version 20211105-signoff (November 5, 2021),
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https://github.com/riscv/riscv-isa-manual/releases/download/draft-20211105-c30284b/riscv-privileged.pdf
4141
42-
.. [RISC-V-DEBUG] RISC-V External Debug Support, version 1.0.0, 2021-10-07,
43-
https://github.com/riscv/riscv-debug-spec/blob/master/riscv-debug-stable.pdf
42+
.. [RISC-V-DEBUG] RISC-V Debug Support, version 1.0.0-STABLE, fe3d1e65efed4b56574c50867830c3c499f9b18c,
43+
https://github.com/riscv/riscv-debug-spec/blob/b659d7dc7f578e1a2a76f9e62a5eec0f2d80045c/riscv-debug-stable.pdf
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45-
.. [RISC-V-SMCLIC] "Smclic" Core-Local Interrupt Controller (CLIC) RISC-V Privileged Architecture Extension, version 0.9-draft, 12/21/2021,
46-
https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.pdf
45+
.. [RISC-V-SMCLIC] "Smclic" Core-Local Interrupt Controller (CLIC) RISC-V Privileged Architecture Extension, version 0.9-draft, 2/15/2022,
46+
https://raw.githubusercontent.com/riscv/riscv-fast-interrupt/0b0083ee0af0cd88d59cdcf81e89cd3f9859e9ad/clic.pdf
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.. [RISC-V-ZBA_ZBB_ZBC_ZBS] RISC-V Bit Manipulation ISA-extensions, Version 1.0.0-38-g865e7a7, 2021-06-28,
4949
https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0-38-g865e7a7.pdf
@@ -57,7 +57,7 @@ It follows these specifications:
5757
.. [OPENHW-OBI] OpenHW Open Bus Interface (OBI) protocol, version 1.2,
5858
https://github.com/openhwgroup/core-v-docs/blob/master/cores/obi/OBI-v1.2.pdf
5959
60-
.. [OPENHW-XIF] OpenHW eXtension Interface, revision fa77b73e,
60+
.. [OPENHW-XIF] OpenHW eXtension Interface, revision 458c8a73,
6161
https://docs.openhwgroup.org/projects/openhw-group-core-v-xif/
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.. [SYMBIOTIC-RVFI] Symbiotic EDA RISC-V Formal Interface

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