Merge pull request #617 from davideschiavone/fix_default

fix default assignments

Author: silabs-oysteink

rtl/cv32e40x_cs_registers.sv

@@ -887,7 +887,7 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*;
         CSR_DSCRATCH1: begin
            dscratch1_we = 1'b1;
         end
-
+        default:;
       endcase
     end
 
@@ -1037,6 +1037,7 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*;
           csr_wdata_int = csr_wdata;
           csr_we_int    = 1'b0;
         end
+        default:;
       endcase
     end
   end

rtl/cv32e40x_id_stage.sv

@@ -307,6 +307,7 @@ module cv32e40x_id_stage import cv32e40x_pkg::*;
     unique case (imm_a_mux_sel)
       IMMA_Z:      imm_a = imm_z_type;
       IMMA_ZERO:   imm_a = '0;
+      default:     imm_a = '0;
     endcase
   end
 

rtl/cv32e40x_load_store_unit.sv

@@ -384,6 +384,7 @@ module cv32e40x_load_store_unit import cv32e40x_pkg::*;
           if (trans.addr[0] != 1'b0)
             misaligned_halfword = 1'b1;
         end
+        default:;
       endcase // case (trans.size)
     end
   end