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| 1 | +From 19e094e5c7aaaf375a13424044521701e85c8313 Mon Sep 17 00:00:00 2001 |
| 2 | +From: OPNA2608 < [email protected]> |
| 3 | +Date: Thu, 9 Jan 2025 17:46:25 +0100 |
| 4 | +Subject: [PATCH] Fix usage of NEON intrinsics |
| 5 | + |
| 6 | +--- |
| 7 | + src/common/gsvector_neon.h | 12 ++++++------ |
| 8 | + 1 file changed, 6 insertions(+), 6 deletions(-) |
| 9 | + |
| 10 | +diff --git a/src/common/gsvector_neon.h b/src/common/gsvector_neon.h |
| 11 | +index e4991af5e..61b8dc09b 100644 |
| 12 | +--- a/src/common/gsvector_neon.h |
| 13 | ++++ b/src/common/gsvector_neon.h |
| 14 | +@@ -867,7 +867,7 @@ public: |
| 15 | + |
| 16 | + ALWAYS_INLINE int mask() const |
| 17 | + { |
| 18 | +- const uint32x2_t masks = vshr_n_u32(vreinterpret_u32_s32(v2s), 31); |
| 19 | ++ const uint32x2_t masks = vshr_n_u32(vreinterpret_u32_f32(v2s), 31); |
| 20 | + return (vget_lane_u32(masks, 0) | (vget_lane_u32(masks, 1) << 1)); |
| 21 | + } |
| 22 | + |
| 23 | +@@ -2882,7 +2882,7 @@ public: |
| 24 | + ALWAYS_INLINE GSVector4 gt64(const GSVector4& v) const |
| 25 | + { |
| 26 | + #ifdef CPU_ARCH_ARM64 |
| 27 | +- return GSVector4(vreinterpretq_f32_f64(vcgtq_f64(vreinterpretq_f64_f32(v4s), vreinterpretq_f64_f32(v.v4s)))); |
| 28 | ++ return GSVector4(vreinterpretq_f32_u64(vcgtq_f64(vreinterpretq_f64_f32(v4s), vreinterpretq_f64_f32(v.v4s)))); |
| 29 | + #else |
| 30 | + GSVector4 ret; |
| 31 | + ret.U64[0] = (F64[0] > v.F64[0]) ? 0xFFFFFFFFFFFFFFFFULL : 0; |
| 32 | +@@ -2894,7 +2894,7 @@ public: |
| 33 | + ALWAYS_INLINE GSVector4 eq64(const GSVector4& v) const |
| 34 | + { |
| 35 | + #ifdef CPU_ARCH_ARM64 |
| 36 | +- return GSVector4(vreinterpretq_f32_f64(vceqq_f64(vreinterpretq_f64_f32(v4s), vreinterpretq_f64_f32(v.v4s)))); |
| 37 | ++ return GSVector4(vreinterpretq_f32_u64(vceqq_f64(vreinterpretq_f64_f32(v4s), vreinterpretq_f64_f32(v.v4s)))); |
| 38 | + #else |
| 39 | + GSVector4 ret; |
| 40 | + ret.U64[0] = (F64[0] == v.F64[0]) ? 0xFFFFFFFFFFFFFFFFULL : 0; |
| 41 | +@@ -2906,7 +2906,7 @@ public: |
| 42 | + ALWAYS_INLINE GSVector4 lt64(const GSVector4& v) const |
| 43 | + { |
| 44 | + #ifdef CPU_ARCH_ARM64 |
| 45 | +- return GSVector4(vreinterpretq_f32_f64(vcgtq_f64(vreinterpretq_f64_f32(v4s), vreinterpretq_f64_f32(v.v4s)))); |
| 46 | ++ return GSVector4(vreinterpretq_f32_u64(vcgtq_f64(vreinterpretq_f64_f32(v4s), vreinterpretq_f64_f32(v.v4s)))); |
| 47 | + #else |
| 48 | + GSVector4 ret; |
| 49 | + ret.U64[0] = (F64[0] < v.F64[0]) ? 0xFFFFFFFFFFFFFFFFULL : 0; |
| 50 | +@@ -2918,7 +2918,7 @@ public: |
| 51 | + ALWAYS_INLINE GSVector4 ge64(const GSVector4& v) const |
| 52 | + { |
| 53 | + #ifdef CPU_ARCH_ARM64 |
| 54 | +- return GSVector4(vreinterpretq_f32_f64(vcgeq_f64(vreinterpretq_f64_f32(v4s), vreinterpretq_f64_f32(v.v4s)))); |
| 55 | ++ return GSVector4(vreinterpretq_f32_u64(vcgeq_f64(vreinterpretq_f64_f32(v4s), vreinterpretq_f64_f32(v.v4s)))); |
| 56 | + #else |
| 57 | + GSVector4 ret; |
| 58 | + ret.U64[0] = (F64[0] >= v.F64[0]) ? 0xFFFFFFFFFFFFFFFFULL : 0; |
| 59 | +@@ -2930,7 +2930,7 @@ public: |
| 60 | + ALWAYS_INLINE GSVector4 le64(const GSVector4& v) const |
| 61 | + { |
| 62 | + #ifdef CPU_ARCH_ARM64 |
| 63 | +- return GSVector4(vreinterpretq_f32_f64(vcleq_f64(vreinterpretq_f64_f32(v4s), vreinterpretq_f64_f32(v.v4s)))); |
| 64 | ++ return GSVector4(vreinterpretq_f32_u64(vcleq_f64(vreinterpretq_f64_f32(v4s), vreinterpretq_f64_f32(v.v4s)))); |
| 65 | + #else |
| 66 | + GSVector4 ret; |
| 67 | + ret.U64[0] = (F64[0] <= v.F64[0]) ? 0xFFFFFFFFFFFFFFFFULL : 0; |
| 68 | +-- |
| 69 | +2.47.0 |
| 70 | + |
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