@@ -1701,7 +1701,8 @@ impl<'block, Registers: RegisterAllocator> BrilligBlock<'block, Registers> {
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self . brillig_context . codegen_branch ( left_is_negative. address , |ctx, is_negative| {
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if is_negative {
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- // If right value is greater than the left bit size, return -1
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+ // Assert right value is less than the left bit size.
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+ // We only need to assert this here as the brillig shr opcode implies this constraint.
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let rhs_does_not_overflow = SingleAddrVariable :: new ( ctx. allocate_register ( ) , 1 ) ;
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let lhs_bit_size =
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ctx. make_constant_instruction ( left. bit_size . into ( ) , right. bit_size ) ;
@@ -1711,35 +1712,30 @@ impl<'block, Registers: RegisterAllocator> BrilligBlock<'block, Registers> {
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rhs_does_not_overflow,
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BrilligBinaryOp :: LessThan ,
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) ;
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+ ctx. codegen_constrain ( rhs_does_not_overflow, None ) ;
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- ctx. codegen_branch ( rhs_does_not_overflow. address , |ctx, no_overflow| {
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- if no_overflow {
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- let one = ctx. make_constant_instruction ( 1_u128 . into ( ) , left. bit_size ) ;
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-
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- // computes 2^right
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- let two = ctx. make_constant_instruction ( 2_u128 . into ( ) , left. bit_size ) ;
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- let two_pow = ctx. make_constant_instruction ( 1_u128 . into ( ) , left. bit_size ) ;
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- let right_u32 = SingleAddrVariable :: new ( ctx. allocate_register ( ) , 32 ) ;
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- ctx. cast ( right_u32, right) ;
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- let pow_body = |ctx : & mut BrilligContext < _ , _ > , _: SingleAddrVariable | {
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- ctx. binary_instruction ( two_pow, two, two_pow, BrilligBinaryOp :: Mul ) ;
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- } ;
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- ctx. codegen_for_loop ( None , right_u32. address , None , pow_body) ;
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-
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- // Right shift using division on 1-complement
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- ctx. binary_instruction ( left, one, result, BrilligBinaryOp :: Add ) ;
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- ctx. convert_signed_division ( result, two_pow, result) ;
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- ctx. binary_instruction ( result, one, result, BrilligBinaryOp :: Sub ) ;
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-
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- // Clean-up
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- ctx. deallocate_single_addr ( one) ;
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- ctx. deallocate_single_addr ( two) ;
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- ctx. deallocate_single_addr ( two_pow) ;
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- ctx. deallocate_single_addr ( right_u32) ;
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- } else {
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- ctx. const_instruction ( result, ( ( 1_u128 << left. bit_size ) - 1 ) . into ( ) ) ;
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- }
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- } ) ;
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+ let one = ctx. make_constant_instruction ( 1_u128 . into ( ) , left. bit_size ) ;
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+
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+ // computes 2^right
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+ let two = ctx. make_constant_instruction ( 2_u128 . into ( ) , left. bit_size ) ;
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+ let two_pow = ctx. make_constant_instruction ( 1_u128 . into ( ) , left. bit_size ) ;
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+ let right_u32 = SingleAddrVariable :: new ( ctx. allocate_register ( ) , 32 ) ;
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+ ctx. cast ( right_u32, right) ;
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+ let pow_body = |ctx : & mut BrilligContext < _ , _ > , _: SingleAddrVariable | {
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+ ctx. binary_instruction ( two_pow, two, two_pow, BrilligBinaryOp :: Mul ) ;
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+ } ;
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+ ctx. codegen_for_loop ( None , right_u32. address , None , pow_body) ;
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+
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+ // Right shift using division on 1-complement
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+ ctx. binary_instruction ( left, one, result, BrilligBinaryOp :: Add ) ;
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+ ctx. convert_signed_division ( result, two_pow, result) ;
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+ ctx. binary_instruction ( result, one, result, BrilligBinaryOp :: Sub ) ;
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+
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+ // Clean-up
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+ ctx. deallocate_single_addr ( one) ;
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+ ctx. deallocate_single_addr ( two) ;
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+ ctx. deallocate_single_addr ( two_pow) ;
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+ ctx. deallocate_single_addr ( right_u32) ;
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ctx. deallocate_single_addr ( rhs_does_not_overflow) ;
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} else {
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