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Andy GrossMatt Wagantall
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i2c: qcom: Add Qualcomm I2C drivers
This is a snapshot of the Qualcomm I2C drivers as of msm-3.10 commit acdce027751d5a7488b283f0ce3111f873a5816d (Merge "defconfig: arm64: Enable ONESHOT_SYNC for msm8994") Signed-off-by: Andy Gross <[email protected]>
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Qualcomm I2C controller
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Required properties:
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- reg : Offset and length of the register region for the device named in
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reg-names and has the same index.
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- reg-names : Register region name(s) referenced in reg above
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"qup_phys_addr" : Physical address of QUP register space.
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"bam_phys_addr" : Physical address of BAM for this controller.
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- compatible : should be "qcom,i2c-msm-v2"
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- interrupts : Interrupt number which correspond to the entry with the same
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index in interrupt-names.
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- interrupt-names: QUP core interrupt name(s) referenced in interrupts above
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"qup_irq" : QUP interrupt used by the controller.
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"bam_irq" : BAM interrupt used by the controller.
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- qcom,clk-freq-out : Desired I2C bus clock frequency in Hz
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- qcom,clk-freq-in : Supplied core clock frequency in Hz.
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- qcom,bam-pipe-idx-cons : BAM consumer-pipe index.
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- qcom,bam-pipe-idx-prod : BAM producer-pipe index.
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Required alias:
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- The desired bus-number is specified by an alias with the following format:
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'i2c{n}' where n is the bus number.
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Optional property:
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- qcom,noise-rjct-scl : number of low samples on clock line to consider it low.
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When missing default to 0.
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- qcom,noise-rjct-sda : number of low samples on data line to consider it low.
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When missing default to 0.
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- qcom,bam-disable : disables BAM transfer mode.
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- qcom,master-id : Master-port value used on voting for the clock path.
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Example:
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aliases {
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i2c10 = &i2c_10;
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};
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i2c_10: i2c@f9966000 {
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compatible = "qcom,i2c-msm-v2";
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reg-names = "qup_phys_addr", "bam_phys_addr";
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reg = <0xf9966000 0x1000>,
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<0xf9904000 0x10000>;
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interrupt-names = "qup_irq", "bam_irq";
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interrupts = <0 104 0>, <0 238 0>;
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qcom,clk-freq-out = <100000>;
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qcom,clk-freq-in = <24000000>;
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qcom,noise-rjct-scl = <0>;
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qcom,noise-rjct-sda = <0>;
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qcom,bam-pipe-idx-cons = <18>;
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qcom,bam-pipe-idx-prod = <19>;
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};
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Qualcomm I2C controller
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Required properties:
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- reg : Offset and length of the register region(s) for the device
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For GSBI based controller, GSBI and QUP regions are expected
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For BLSP based controller, QUP region offset is expected
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- reg-names : Register region name(s) referenced in reg above
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BLSP based controller expects QUP region name ("qup_phys_addr")
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GSBI controller expects QUP region name and GSBI region name
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("gsbi_qup_i2c_addr")
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- compatible : should be "qcom,i2c-qup"
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- cell-index : I2C bus number used for this controller
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- interrupts : QUP core interrupt(s). Core may have 1 error interrupt and flags
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for input/output service, or 3 separate interrupts for the 3 services
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- interrupt-names: QUP core interrupt name(s) referenced in interrupts above
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Expected interrupt resource name(s) are: "qup_err_irq", "qup_in_irq",
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and "qup_out_irq"
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- qcom,i2c-bus-freq : desired I2C bus clock frequency is Hz
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Optional property:
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- qcom,noise-rjct-scl : Number of low samples on clock line to consider it low.
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Range of values is 0-3. When missing default to 0.
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- qcom,noise-rjct-sda : Number of low samples on data line to consider it low.
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Range of values is 0-3. When missing default to 0.
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- qcom,i2c-src-freq : Frequency of the source clocking this bus in Hz.
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Divider value is set based on soruce-frequency and
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desired I2C bus frequency. If this value is not
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provided, the source clock is assumed to be running
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at 19.2 MHz.
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- qcom,scl-gpio : I2C clock GPIO number. Required for execution of bus
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recovery procedure.
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- qcom,sda-gpio : I2C data GPIO number. Required for execution of bus
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recovery procedure.
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- qcom,active-only : Vote for core clock when the application processor goes
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to active state and remove that vote when it goes to idle
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state. This flag may improve service time of first i2c
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request at the expense of power consumption. When this
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entry is not present, voting is done by the runtime-pm
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callbacks.
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- qcom,master-id : Master endpoint number used for voting on clocks using
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bus-scaling driver.
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- qcom,clk-ctl-xfer : When present, the clocks's state (prepare_enable/
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unprepare_disable) is controlled by i2c-transaction's
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begining and ending. When missing, the clock's state
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is controlled by runtime-pm events.
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Example:
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i2c_3: i2c@f9966000 {
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cell-index = <3>;
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compatible = "qcom,i2c-qup";
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reg = <0xf9966000 0x1000>;
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reg-names = "qup_phys_addr";
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interrupts = <0 104 0>;
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qcom,noise-rjct-scl = <1>;
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qcom,noise-rjct-sda = <1>;
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interrupt-names = "qup_err_intr";
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qcom,i2c-bus-freq = <100000>;
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qcom,i2c-src-freq = <24000000>;
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qcom,clk-ctl-xfer;
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qcom,scl-gpio = <&msmgpio 7 0>;
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qcom,sda-gpio = <&msmgpio 6 0>;
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};

drivers/i2c/busses/Kconfig

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This driver can also be built as a module. If so, the module
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will be called i2c-rcar.
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config I2C_MSM_QUP
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tristate "I2C_QUP"
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depends on ARCH_MSM
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help
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If you say yes to this option, support will be included for the
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built-in I2C interface on the MSM family processors.
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config I2C_MSM_V2
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tristate "I2C_MSM_V2"
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depends on ARCH_MSM
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help
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If you say yes to this option, support will be included for the
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built-in I2C interface and its DMA engine on the MSM family
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processors.
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This driver can also be built as a module. If so, the module
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will be called i2c-msm-v2.
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comment "External I2C/SMBus adapter drivers"
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config I2C_DIOLAN_U2C

drivers/i2c/busses/Makefile

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obj-$(CONFIG_I2C_XILINX) += i2c-xiic.o
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obj-$(CONFIG_I2C_XLR) += i2c-xlr.o
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obj-$(CONFIG_I2C_RCAR) += i2c-rcar.o
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obj-$(CONFIG_I2C_MSM_QUP) += i2c-msm-qup.o
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obj-$(CONFIG_I2C_MSM_V2) += i2c-msm-v2.o
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# External I2C/SMBus adapter drivers
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obj-$(CONFIG_I2C_DIOLAN_U2C) += i2c-diolan-u2c.o

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