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Merge tag 'mlx5-updates-2021-12-14' of git://git.kernel.org/pub/scm/linux/kernel/git/saeed/linux
Saed Mahameed says: ==================== mlx5-updates-2021-12-14 Parsing Infrastructure for TC actions: The series introduce a TC action infrastructure to help parsing TC actions in a generic way for both FDB and NIC rules. To help maintain the parsing code of TC actions, we the parsing code to action parser per action TC type in separate files, instead of having one big switch case loop, duplicated between FDB and NIC parsers as before this patchset. Each TC flow_action->id is represented by a dedicated mlx5e_tc_act handler which has callbacks to check if the specific action is offload supported and to parse the specific action. We move each case (TC action) handling into the specific handler, which is responsible for parsing and determining if the action is supported. ==================== Signed-off-by: David S. Miller <[email protected]>
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‎drivers/net/ethernet/mellanox/mlx5/core/Makefile‎

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Original file line numberDiff line numberDiff line change
@@ -46,6 +46,15 @@ mlx5_core-$(CONFIG_MLX5_CLS_ACT) += en_tc.o en/rep/tc.o en/rep/neigh.o \
4646
en/tc_tun_vxlan.o en/tc_tun_gre.o en/tc_tun_geneve.o \
4747
en/tc_tun_mplsoudp.o diag/en_tc_tracepoint.o \
4848
en/tc/post_act.o en/tc/int_port.o
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mlx5_core-$(CONFIG_MLX5_CLS_ACT) += en/tc/act/act.o en/tc/act/drop.o en/tc/act/trap.o \
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en/tc/act/accept.o en/tc/act/mark.o en/tc/act/goto.o \
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en/tc/act/tun.o en/tc/act/csum.o en/tc/act/pedit.o \
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en/tc/act/vlan.o en/tc/act/vlan_mangle.o en/tc/act/mpls.o \
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en/tc/act/mirred.o en/tc/act/mirred_nic.o \
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en/tc/act/ct.o en/tc/act/sample.o en/tc/act/ptype.o \
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en/tc/act/redirect_ingress.o
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4958
mlx5_core-$(CONFIG_MLX5_TC_CT) += en/tc_ct.o
5059
mlx5_core-$(CONFIG_MLX5_TC_SAMPLE) += en/tc/sample.o
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‎drivers/net/ethernet/mellanox/mlx5/core/en/tc/act/accept.c‎

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// SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
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// Copyright (c) 2021, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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#include "act.h"
5+
#include "en/tc_priv.h"
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static bool
8+
tc_act_can_offload_accept(struct mlx5e_tc_act_parse_state *parse_state,
9+
const struct flow_action_entry *act,
10+
int act_index)
11+
{
12+
return true;
13+
}
14+
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static int
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tc_act_parse_accept(struct mlx5e_tc_act_parse_state *parse_state,
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const struct flow_action_entry *act,
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struct mlx5e_priv *priv,
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struct mlx5_flow_attr *attr)
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{
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attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
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MLX5_FLOW_CONTEXT_ACTION_COUNT;
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attr->flags |= MLX5_ESW_ATTR_FLAG_ACCEPT;
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return 0;
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}
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struct mlx5e_tc_act mlx5e_tc_act_accept = {
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.can_offload = tc_act_can_offload_accept,
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.parse_action = tc_act_parse_accept,
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};

‎drivers/net/ethernet/mellanox/mlx5/core/en/tc/act/act.c‎

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// SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
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// Copyright (c) 2021, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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#include "act.h"
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#include "en/tc_priv.h"
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#include "mlx5_core.h"
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/* Must be aligned with enum flow_action_id. */
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static struct mlx5e_tc_act *tc_acts_fdb[NUM_FLOW_ACTIONS] = {
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&mlx5e_tc_act_accept,
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&mlx5e_tc_act_drop,
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&mlx5e_tc_act_trap,
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&mlx5e_tc_act_goto,
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&mlx5e_tc_act_mirred,
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&mlx5e_tc_act_mirred,
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&mlx5e_tc_act_redirect_ingress,
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NULL, /* FLOW_ACTION_MIRRED_INGRESS, */
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&mlx5e_tc_act_vlan,
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&mlx5e_tc_act_vlan,
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&mlx5e_tc_act_vlan_mangle,
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&mlx5e_tc_act_tun_encap,
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&mlx5e_tc_act_tun_decap,
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&mlx5e_tc_act_pedit,
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&mlx5e_tc_act_pedit,
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&mlx5e_tc_act_csum,
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NULL, /* FLOW_ACTION_MARK, */
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&mlx5e_tc_act_ptype,
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NULL, /* FLOW_ACTION_PRIORITY, */
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NULL, /* FLOW_ACTION_WAKE, */
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NULL, /* FLOW_ACTION_QUEUE, */
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&mlx5e_tc_act_sample,
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NULL, /* FLOW_ACTION_POLICE, */
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&mlx5e_tc_act_ct,
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NULL, /* FLOW_ACTION_CT_METADATA, */
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&mlx5e_tc_act_mpls_push,
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&mlx5e_tc_act_mpls_pop,
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};
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/* Must be aligned with enum flow_action_id. */
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static struct mlx5e_tc_act *tc_acts_nic[NUM_FLOW_ACTIONS] = {
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&mlx5e_tc_act_accept,
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&mlx5e_tc_act_drop,
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NULL, /* FLOW_ACTION_TRAP, */
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&mlx5e_tc_act_goto,
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&mlx5e_tc_act_mirred_nic,
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NULL, /* FLOW_ACTION_MIRRED, */
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NULL, /* FLOW_ACTION_REDIRECT_INGRESS, */
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NULL, /* FLOW_ACTION_MIRRED_INGRESS, */
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NULL, /* FLOW_ACTION_VLAN_PUSH, */
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NULL, /* FLOW_ACTION_VLAN_POP, */
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NULL, /* FLOW_ACTION_VLAN_MANGLE, */
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NULL, /* FLOW_ACTION_TUNNEL_ENCAP, */
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NULL, /* FLOW_ACTION_TUNNEL_DECAP, */
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&mlx5e_tc_act_pedit,
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&mlx5e_tc_act_pedit,
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&mlx5e_tc_act_csum,
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&mlx5e_tc_act_mark,
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NULL, /* FLOW_ACTION_PTYPE, */
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NULL, /* FLOW_ACTION_PRIORITY, */
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NULL, /* FLOW_ACTION_WAKE, */
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NULL, /* FLOW_ACTION_QUEUE, */
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NULL, /* FLOW_ACTION_SAMPLE, */
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NULL, /* FLOW_ACTION_POLICE, */
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&mlx5e_tc_act_ct,
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};
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/**
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* mlx5e_tc_act_get() - Get an action parser for an action id.
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* @act_id: Flow action id.
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* @ns_type: flow namespace type.
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*/
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struct mlx5e_tc_act *
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mlx5e_tc_act_get(enum flow_action_id act_id,
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enum mlx5_flow_namespace_type ns_type)
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{
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struct mlx5e_tc_act **tc_acts;
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tc_acts = ns_type == MLX5_FLOW_NAMESPACE_FDB ? tc_acts_fdb : tc_acts_nic;
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return tc_acts[act_id];
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}
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/**
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* mlx5e_tc_act_init_parse_state() - Init a new parse_state.
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* @parse_state: Parsing state.
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* @flow: mlx5e tc flow being handled.
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* @flow_action: flow action to parse.
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* @extack: to set an error msg.
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*
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* The same parse_state should be passed to action parsers
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* for tracking the current parsing state.
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*/
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void
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mlx5e_tc_act_init_parse_state(struct mlx5e_tc_act_parse_state *parse_state,
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struct mlx5e_tc_flow *flow,
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struct flow_action *flow_action,
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struct netlink_ext_ack *extack)
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{
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memset(parse_state, 0, sizeof(*parse_state));
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parse_state->flow = flow;
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parse_state->num_actions = flow_action->num_entries;
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parse_state->extack = extack;
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}

‎drivers/net/ethernet/mellanox/mlx5/core/en/tc/act/act.h‎

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/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
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/* Copyright (c) 2021, NVIDIA CORPORATION & AFFILIATES. All rights reserved. */
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#ifndef __MLX5_EN_TC_ACT_H__
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#define __MLX5_EN_TC_ACT_H__
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#include <net/tc_act/tc_pedit.h>
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#include <net/flow_offload.h>
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#include <linux/netlink.h>
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#include "eswitch.h"
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#include "pedit.h"
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struct mlx5_flow_attr;
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struct mlx5e_tc_act_parse_state {
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unsigned int num_actions;
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struct mlx5e_tc_flow *flow;
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struct netlink_ext_ack *extack;
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bool encap;
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bool decap;
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bool mpls_push;
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bool ptype_host;
23+
const struct ip_tunnel_info *tun_info;
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struct pedit_headers_action hdrs[__PEDIT_CMD_MAX];
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int ifindexes[MLX5_MAX_FLOW_FWD_VPORTS];
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int if_count;
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struct mlx5_tc_ct_priv *ct_priv;
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};
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struct mlx5e_tc_act {
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bool (*can_offload)(struct mlx5e_tc_act_parse_state *parse_state,
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const struct flow_action_entry *act,
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int act_index);
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int (*parse_action)(struct mlx5e_tc_act_parse_state *parse_state,
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const struct flow_action_entry *act,
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struct mlx5e_priv *priv,
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struct mlx5_flow_attr *attr);
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int (*post_parse)(struct mlx5e_tc_act_parse_state *parse_state,
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struct mlx5e_priv *priv,
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struct mlx5_flow_attr *attr);
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};
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extern struct mlx5e_tc_act mlx5e_tc_act_drop;
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extern struct mlx5e_tc_act mlx5e_tc_act_trap;
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extern struct mlx5e_tc_act mlx5e_tc_act_accept;
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extern struct mlx5e_tc_act mlx5e_tc_act_mark;
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extern struct mlx5e_tc_act mlx5e_tc_act_goto;
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extern struct mlx5e_tc_act mlx5e_tc_act_tun_encap;
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extern struct mlx5e_tc_act mlx5e_tc_act_tun_decap;
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extern struct mlx5e_tc_act mlx5e_tc_act_csum;
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extern struct mlx5e_tc_act mlx5e_tc_act_pedit;
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extern struct mlx5e_tc_act mlx5e_tc_act_vlan;
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extern struct mlx5e_tc_act mlx5e_tc_act_vlan_mangle;
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extern struct mlx5e_tc_act mlx5e_tc_act_mpls_push;
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extern struct mlx5e_tc_act mlx5e_tc_act_mpls_pop;
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extern struct mlx5e_tc_act mlx5e_tc_act_mirred;
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extern struct mlx5e_tc_act mlx5e_tc_act_mirred_nic;
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extern struct mlx5e_tc_act mlx5e_tc_act_ct;
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extern struct mlx5e_tc_act mlx5e_tc_act_sample;
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extern struct mlx5e_tc_act mlx5e_tc_act_ptype;
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extern struct mlx5e_tc_act mlx5e_tc_act_redirect_ingress;
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struct mlx5e_tc_act *
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mlx5e_tc_act_get(enum flow_action_id act_id,
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enum mlx5_flow_namespace_type ns_type);
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void
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mlx5e_tc_act_init_parse_state(struct mlx5e_tc_act_parse_state *parse_state,
71+
struct mlx5e_tc_flow *flow,
72+
struct flow_action *flow_action,
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struct netlink_ext_ack *extack);
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#endif /* __MLX5_EN_TC_ACT_H__ */

‎drivers/net/ethernet/mellanox/mlx5/core/en/tc/act/csum.c‎

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// SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
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// Copyright (c) 2021, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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#include <linux/tc_act/tc_csum.h>
5+
#include "act.h"
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#include "en/tc_priv.h"
7+
8+
static bool
9+
csum_offload_supported(struct mlx5e_priv *priv,
10+
u32 action,
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u32 update_flags,
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struct netlink_ext_ack *extack)
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{
14+
u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
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TCA_CSUM_UPDATE_FLAG_UDP;
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/* The HW recalcs checksums only if re-writing headers */
18+
if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
19+
NL_SET_ERR_MSG_MOD(extack,
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"TC csum action is only offloaded with pedit");
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netdev_warn(priv->netdev,
22+
"TC csum action is only offloaded with pedit\n");
23+
return false;
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}
25+
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if (update_flags & ~prot_flags) {
27+
NL_SET_ERR_MSG_MOD(extack,
28+
"can't offload TC csum action for some header/s");
29+
netdev_warn(priv->netdev,
30+
"can't offload TC csum action for some header/s - flags %#x\n",
31+
update_flags);
32+
return false;
33+
}
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return true;
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}
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38+
static bool
39+
tc_act_can_offload_csum(struct mlx5e_tc_act_parse_state *parse_state,
40+
const struct flow_action_entry *act,
41+
int act_index)
42+
{
43+
struct mlx5e_tc_flow *flow = parse_state->flow;
44+
45+
return csum_offload_supported(flow->priv, flow->attr->action,
46+
act->csum_flags, parse_state->extack);
47+
}
48+
49+
static int
50+
tc_act_parse_csum(struct mlx5e_tc_act_parse_state *parse_state,
51+
const struct flow_action_entry *act,
52+
struct mlx5e_priv *priv,
53+
struct mlx5_flow_attr *attr)
54+
{
55+
return 0;
56+
}
57+
58+
struct mlx5e_tc_act mlx5e_tc_act_csum = {
59+
.can_offload = tc_act_can_offload_csum,
60+
.parse_action = tc_act_parse_csum,
61+
};

‎drivers/net/ethernet/mellanox/mlx5/core/en/tc/act/ct.c‎

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// SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
2+
// Copyright (c) 2021, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
3+
4+
#include "act.h"
5+
#include "en/tc_priv.h"
6+
#include "en/tc_ct.h"
7+
8+
static bool
9+
tc_act_can_offload_ct(struct mlx5e_tc_act_parse_state *parse_state,
10+
const struct flow_action_entry *act,
11+
int act_index)
12+
{
13+
struct netlink_ext_ack *extack = parse_state->extack;
14+
15+
if (flow_flag_test(parse_state->flow, SAMPLE)) {
16+
NL_SET_ERR_MSG_MOD(extack,
17+
"Sample action with connection tracking is not supported");
18+
return false;
19+
}
20+
21+
return true;
22+
}
23+
24+
static int
25+
tc_act_parse_ct(struct mlx5e_tc_act_parse_state *parse_state,
26+
const struct flow_action_entry *act,
27+
struct mlx5e_priv *priv,
28+
struct mlx5_flow_attr *attr)
29+
{
30+
int err;
31+
32+
err = mlx5_tc_ct_parse_action(parse_state->ct_priv, attr,
33+
&attr->parse_attr->mod_hdr_acts,
34+
act, parse_state->extack);
35+
if (err)
36+
return err;
37+
38+
flow_flag_set(parse_state->flow, CT);
39+
40+
if (mlx5e_is_eswitch_flow(parse_state->flow))
41+
attr->esw_attr->split_count = attr->esw_attr->out_count;
42+
43+
return 0;
44+
}
45+
46+
struct mlx5e_tc_act mlx5e_tc_act_ct = {
47+
.can_offload = tc_act_can_offload_ct,
48+
.parse_action = tc_act_parse_ct,
49+
};
50+

‎drivers/net/ethernet/mellanox/mlx5/core/en/tc/act/drop.c‎

Lines changed: 30 additions & 0 deletions
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1+
// SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
2+
// Copyright (c) 2021, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
3+
4+
#include "act.h"
5+
#include "en/tc_priv.h"
6+
7+
static bool
8+
tc_act_can_offload_drop(struct mlx5e_tc_act_parse_state *parse_state,
9+
const struct flow_action_entry *act,
10+
int act_index)
11+
{
12+
return true;
13+
}
14+
15+
static int
16+
tc_act_parse_drop(struct mlx5e_tc_act_parse_state *parse_state,
17+
const struct flow_action_entry *act,
18+
struct mlx5e_priv *priv,
19+
struct mlx5_flow_attr *attr)
20+
{
21+
attr->action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
22+
MLX5_FLOW_CONTEXT_ACTION_COUNT;
23+
24+
return 0;
25+
}
26+
27+
struct mlx5e_tc_act mlx5e_tc_act_drop = {
28+
.can_offload = tc_act_can_offload_drop,
29+
.parse_action = tc_act_parse_drop,
30+
};

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