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LoongArch: Add BPF JIT support
BPF programs are normally handled by a BPF interpreter, add BPF JIT support for LoongArch to allow the kernel to generate native code when a program is loaded into the kernel. This will significantly speed-up processing of BPF programs. Co-developed-by: Youling Tang <[email protected]> Signed-off-by: Youling Tang <[email protected]> Signed-off-by: Tiezhu Yang <[email protected]> Signed-off-by: Huacai Chen <[email protected]>
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‎arch/loongarch/Kbuild‎

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@@ -1,5 +1,6 @@
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obj-y += kernel/
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obj-y += mm/
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obj-y += net/
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obj-y += vdso/
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# for cleaning

‎arch/loongarch/Kconfig‎

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@@ -87,6 +87,7 @@ config LOONGARCH
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select HAVE_CONTEXT_TRACKING_USER
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select HAVE_DEBUG_STACKOVERFLOW
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select HAVE_DMA_CONTIGUOUS
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select HAVE_EBPF_JIT
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select HAVE_EXIT_THREAD
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select HAVE_FAST_GUP
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select HAVE_GENERIC_VDSO

‎arch/loongarch/include/asm/inst.h‎

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@@ -345,4 +345,225 @@ static inline bool unsigned_imm_check(unsigned long val, unsigned int bit)
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return val < (1UL << bit);
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}
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#define DEF_EMIT_REG0I26_FORMAT(NAME, OP) \
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static inline void emit_##NAME(union loongarch_instruction *insn, \
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int offset) \
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{ \
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unsigned int immediate_l, immediate_h; \
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\
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immediate_l = offset & 0xffff; \
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offset >>= 16; \
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immediate_h = offset & 0x3ff; \
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\
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insn->reg0i26_format.opcode = OP; \
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insn->reg0i26_format.immediate_l = immediate_l; \
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insn->reg0i26_format.immediate_h = immediate_h; \
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}
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DEF_EMIT_REG0I26_FORMAT(b, b_op)
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#define DEF_EMIT_REG1I20_FORMAT(NAME, OP) \
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static inline void emit_##NAME(union loongarch_instruction *insn, \
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enum loongarch_gpr rd, int imm) \
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{ \
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insn->reg1i20_format.opcode = OP; \
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insn->reg1i20_format.immediate = imm; \
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insn->reg1i20_format.rd = rd; \
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}
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DEF_EMIT_REG1I20_FORMAT(lu12iw, lu12iw_op)
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DEF_EMIT_REG1I20_FORMAT(lu32id, lu32id_op)
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DEF_EMIT_REG1I20_FORMAT(pcaddu18i, pcaddu18i_op)
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#define DEF_EMIT_REG2_FORMAT(NAME, OP) \
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static inline void emit_##NAME(union loongarch_instruction *insn, \
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enum loongarch_gpr rd, \
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enum loongarch_gpr rj) \
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{ \
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insn->reg2_format.opcode = OP; \
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insn->reg2_format.rd = rd; \
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insn->reg2_format.rj = rj; \
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}
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DEF_EMIT_REG2_FORMAT(revb2h, revb2h_op)
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DEF_EMIT_REG2_FORMAT(revb2w, revb2w_op)
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DEF_EMIT_REG2_FORMAT(revbd, revbd_op)
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#define DEF_EMIT_REG2I5_FORMAT(NAME, OP) \
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static inline void emit_##NAME(union loongarch_instruction *insn, \
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enum loongarch_gpr rd, \
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enum loongarch_gpr rj, \
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int imm) \
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{ \
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insn->reg2i5_format.opcode = OP; \
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insn->reg2i5_format.immediate = imm; \
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insn->reg2i5_format.rd = rd; \
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insn->reg2i5_format.rj = rj; \
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}
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DEF_EMIT_REG2I5_FORMAT(slliw, slliw_op)
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DEF_EMIT_REG2I5_FORMAT(srliw, srliw_op)
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DEF_EMIT_REG2I5_FORMAT(sraiw, sraiw_op)
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#define DEF_EMIT_REG2I6_FORMAT(NAME, OP) \
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static inline void emit_##NAME(union loongarch_instruction *insn, \
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enum loongarch_gpr rd, \
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enum loongarch_gpr rj, \
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int imm) \
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{ \
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insn->reg2i6_format.opcode = OP; \
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insn->reg2i6_format.immediate = imm; \
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insn->reg2i6_format.rd = rd; \
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insn->reg2i6_format.rj = rj; \
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}
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DEF_EMIT_REG2I6_FORMAT(sllid, sllid_op)
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DEF_EMIT_REG2I6_FORMAT(srlid, srlid_op)
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DEF_EMIT_REG2I6_FORMAT(sraid, sraid_op)
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#define DEF_EMIT_REG2I12_FORMAT(NAME, OP) \
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static inline void emit_##NAME(union loongarch_instruction *insn, \
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enum loongarch_gpr rd, \
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enum loongarch_gpr rj, \
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int imm) \
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{ \
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insn->reg2i12_format.opcode = OP; \
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insn->reg2i12_format.immediate = imm; \
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insn->reg2i12_format.rd = rd; \
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insn->reg2i12_format.rj = rj; \
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}
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DEF_EMIT_REG2I12_FORMAT(addiw, addiw_op)
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DEF_EMIT_REG2I12_FORMAT(addid, addid_op)
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DEF_EMIT_REG2I12_FORMAT(lu52id, lu52id_op)
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DEF_EMIT_REG2I12_FORMAT(andi, andi_op)
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DEF_EMIT_REG2I12_FORMAT(ori, ori_op)
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DEF_EMIT_REG2I12_FORMAT(xori, xori_op)
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DEF_EMIT_REG2I12_FORMAT(ldbu, ldbu_op)
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DEF_EMIT_REG2I12_FORMAT(ldhu, ldhu_op)
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DEF_EMIT_REG2I12_FORMAT(ldwu, ldwu_op)
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DEF_EMIT_REG2I12_FORMAT(ldd, ldd_op)
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DEF_EMIT_REG2I12_FORMAT(stb, stb_op)
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DEF_EMIT_REG2I12_FORMAT(sth, sth_op)
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DEF_EMIT_REG2I12_FORMAT(stw, stw_op)
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DEF_EMIT_REG2I12_FORMAT(std, std_op)
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#define DEF_EMIT_REG2I14_FORMAT(NAME, OP) \
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static inline void emit_##NAME(union loongarch_instruction *insn, \
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enum loongarch_gpr rd, \
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enum loongarch_gpr rj, \
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int imm) \
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{ \
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insn->reg2i14_format.opcode = OP; \
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insn->reg2i14_format.immediate = imm; \
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insn->reg2i14_format.rd = rd; \
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insn->reg2i14_format.rj = rj; \
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}
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DEF_EMIT_REG2I14_FORMAT(llw, llw_op)
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DEF_EMIT_REG2I14_FORMAT(scw, scw_op)
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DEF_EMIT_REG2I14_FORMAT(lld, lld_op)
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DEF_EMIT_REG2I14_FORMAT(scd, scd_op)
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DEF_EMIT_REG2I14_FORMAT(ldptrw, ldptrw_op)
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DEF_EMIT_REG2I14_FORMAT(stptrw, stptrw_op)
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DEF_EMIT_REG2I14_FORMAT(ldptrd, ldptrd_op)
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DEF_EMIT_REG2I14_FORMAT(stptrd, stptrd_op)
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#define DEF_EMIT_REG2I16_FORMAT(NAME, OP) \
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static inline void emit_##NAME(union loongarch_instruction *insn, \
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enum loongarch_gpr rj, \
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enum loongarch_gpr rd, \
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int offset) \
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{ \
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insn->reg2i16_format.opcode = OP; \
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insn->reg2i16_format.immediate = offset; \
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insn->reg2i16_format.rj = rj; \
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insn->reg2i16_format.rd = rd; \
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}
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DEF_EMIT_REG2I16_FORMAT(beq, beq_op)
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DEF_EMIT_REG2I16_FORMAT(bne, bne_op)
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DEF_EMIT_REG2I16_FORMAT(blt, blt_op)
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DEF_EMIT_REG2I16_FORMAT(bge, bge_op)
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DEF_EMIT_REG2I16_FORMAT(bltu, bltu_op)
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DEF_EMIT_REG2I16_FORMAT(bgeu, bgeu_op)
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DEF_EMIT_REG2I16_FORMAT(jirl, jirl_op)
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#define DEF_EMIT_REG2BSTRD_FORMAT(NAME, OP) \
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static inline void emit_##NAME(union loongarch_instruction *insn, \
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enum loongarch_gpr rd, \
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enum loongarch_gpr rj, \
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int msbd, \
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int lsbd) \
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{ \
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insn->reg2bstrd_format.opcode = OP; \
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insn->reg2bstrd_format.msbd = msbd; \
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insn->reg2bstrd_format.lsbd = lsbd; \
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insn->reg2bstrd_format.rj = rj; \
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insn->reg2bstrd_format.rd = rd; \
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}
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DEF_EMIT_REG2BSTRD_FORMAT(bstrpickd, bstrpickd_op)
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#define DEF_EMIT_REG3_FORMAT(NAME, OP) \
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static inline void emit_##NAME(union loongarch_instruction *insn, \
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enum loongarch_gpr rd, \
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enum loongarch_gpr rj, \
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enum loongarch_gpr rk) \
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{ \
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insn->reg3_format.opcode = OP; \
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insn->reg3_format.rd = rd; \
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insn->reg3_format.rj = rj; \
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insn->reg3_format.rk = rk; \
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}
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DEF_EMIT_REG3_FORMAT(addd, addd_op)
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DEF_EMIT_REG3_FORMAT(subd, subd_op)
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DEF_EMIT_REG3_FORMAT(muld, muld_op)
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DEF_EMIT_REG3_FORMAT(divdu, divdu_op)
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DEF_EMIT_REG3_FORMAT(moddu, moddu_op)
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DEF_EMIT_REG3_FORMAT(and, and_op)
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DEF_EMIT_REG3_FORMAT(or, or_op)
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DEF_EMIT_REG3_FORMAT(xor, xor_op)
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DEF_EMIT_REG3_FORMAT(sllw, sllw_op)
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DEF_EMIT_REG3_FORMAT(slld, slld_op)
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DEF_EMIT_REG3_FORMAT(srlw, srlw_op)
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DEF_EMIT_REG3_FORMAT(srld, srld_op)
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DEF_EMIT_REG3_FORMAT(sraw, sraw_op)
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DEF_EMIT_REG3_FORMAT(srad, srad_op)
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DEF_EMIT_REG3_FORMAT(ldxbu, ldxbu_op)
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DEF_EMIT_REG3_FORMAT(ldxhu, ldxhu_op)
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DEF_EMIT_REG3_FORMAT(ldxwu, ldxwu_op)
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DEF_EMIT_REG3_FORMAT(ldxd, ldxd_op)
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DEF_EMIT_REG3_FORMAT(stxb, stxb_op)
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DEF_EMIT_REG3_FORMAT(stxh, stxh_op)
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DEF_EMIT_REG3_FORMAT(stxw, stxw_op)
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DEF_EMIT_REG3_FORMAT(stxd, stxd_op)
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DEF_EMIT_REG3_FORMAT(amaddw, amaddw_op)
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DEF_EMIT_REG3_FORMAT(amaddd, amaddd_op)
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DEF_EMIT_REG3_FORMAT(amandw, amandw_op)
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DEF_EMIT_REG3_FORMAT(amandd, amandd_op)
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DEF_EMIT_REG3_FORMAT(amorw, amorw_op)
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DEF_EMIT_REG3_FORMAT(amord, amord_op)
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DEF_EMIT_REG3_FORMAT(amxorw, amxorw_op)
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DEF_EMIT_REG3_FORMAT(amxord, amxord_op)
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DEF_EMIT_REG3_FORMAT(amswapw, amswapw_op)
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DEF_EMIT_REG3_FORMAT(amswapd, amswapd_op)
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#define DEF_EMIT_REG3SA2_FORMAT(NAME, OP) \
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static inline void emit_##NAME(union loongarch_instruction *insn, \
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enum loongarch_gpr rd, \
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enum loongarch_gpr rj, \
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enum loongarch_gpr rk, \
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int imm) \
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{ \
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insn->reg3sa2_format.opcode = OP; \
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insn->reg3sa2_format.immediate = imm; \
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insn->reg3sa2_format.rd = rd; \
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insn->reg3sa2_format.rj = rj; \
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insn->reg3sa2_format.rk = rk; \
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}
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DEF_EMIT_REG3SA2_FORMAT(alsld, alsld_op)
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#endif /* _ASM_INST_H */

‎arch/loongarch/include/uapi/asm/bpf_perf_event.h‎

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/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
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#ifndef _UAPI__ASM_BPF_PERF_EVENT_H__
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#define _UAPI__ASM_BPF_PERF_EVENT_H__
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#include <linux/ptrace.h>
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typedef struct user_pt_regs bpf_user_pt_regs_t;
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#endif /* _UAPI__ASM_BPF_PERF_EVENT_H__ */

‎arch/loongarch/net/Makefile‎

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# SPDX-License-Identifier: GPL-2.0-only
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#
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# Makefile for arch/loongarch/net
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#
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# Copyright (C) 2022 Loongson Technology Corporation Limited
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#
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obj-$(CONFIG_BPF_JIT) += bpf_jit.o

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