Do not gen empty param sv (#498)

Author: mkorbel1

lib/src/synthesizers/systemverilog.dart

@@ -102,7 +102,7 @@ class SystemVerilogSynthesizer extends Synthesizer {
     final connectionsStr = connections.join(',');
 
     var parameterString = '';
-    if (parameters != null) {
+    if (parameters != null && parameters.isNotEmpty) {
       final parameterContents =
           parameters.entries.map((e) => '.${e.key}(${e.value})').join(',');
       parameterString = '#($parameterContents)';
@@ -485,7 +485,7 @@ class _SystemVerilogSynthesisResult extends SynthesisResult {
   String? _verilogParameters(Module module) {
     if (module is SystemVerilog) {
       final defParams = module.definitionParameters;
-      if (defParams == null) {
+      if (defParams == null || defParams.isEmpty) {
         return null;
       }
 

test/sv_param_passthrough_test.dart

@@ -114,6 +114,35 @@ class LeafNodeExternal extends ModWithParamPassthrough {
   String? definitionVerilog(String definitionType) => '';
 }
 
+class TopForEmptyParams extends ModWithParamPassthrough {
+  Logic get b => output('b');
+  TopForEmptyParams(Logic a,
+      {super.definitionName = 'top_for_empty',
+      super.instantiationParameters = const {},
+      super.name = 'top'})
+      : super([]) {
+    a = addInput('a', a, width: 8);
+    addOutput('b', width: 8);
+    b <= LeafNodeExternalEmptyParams(a).b;
+  }
+}
+
+class LeafNodeExternalEmptyParams extends ModWithParamPassthrough {
+  Logic get b => output('b');
+  LeafNodeExternalEmptyParams(Logic a,
+      {super.definitionName = 'leaf_node',
+      super.instantiationParameters = const {},
+      super.name = 'leaf'})
+      : super([]) {
+    a = addInput('a', a, width: 8);
+    addOutput('b', width: 8);
+  }
+
+  // leaf node should not generate any SV, like external
+  @override
+  String? definitionVerilog(String definitionType) => '';
+}
+
 void main() {
   test('passthrough params custom system verilog', () async {
     final mod = Top(Logic(width: 8));
@@ -128,4 +157,12 @@ void main() {
       'test/sv_param_passthrough.sv', // include external SV
     ]);
   });
+
+  test('empty params does include param # in generated system verilog',
+      () async {
+    final mod = TopForEmptyParams(Logic(width: 8));
+    await mod.build();
+    final sv = mod.generateSynth();
+    expect(sv.contains('#'), isFalse);
+  });
 }