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jonathandavies-armjonathandavies-arm
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arm64: Add Sve2 Subtract functions (#117318)
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10 files changed

+1335
-5
lines changed

10 files changed

+1335
-5
lines changed

‎src/coreclr/jit/emitarm64.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -555,7 +555,7 @@ static code_t insEncodeReg3Scale(bool isScaled);
555555
// Returns the encoding to select the 1/2/4/8 byte elemsize for an Arm64 SVE vector instruction
556556
static code_t insEncodeSveElemsize(emitAttr size);
557557

558-
// Returns the encoding to select the 1/2/4/8 byte elemsize for an Arm64 Sve vector instruction
558+
// Returns the encoding to select the 1/2/4 byte elemsize for an Arm64 Sve narrowing vector instruction
559559
static code_t insEncodeNarrowingSveElemsize(emitAttr size);
560560

561561
// Returns the encoding to select the 1/2/4/8 byte elemsize for an Arm64 Sve vector instruction

‎src/coreclr/jit/emitarm64sve.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7441,7 +7441,7 @@ void emitter::emitIns_PRFOP_R_R_I(instruction ins,
74417441

74427442
/*****************************************************************************
74437443
*
7444-
* Returns the encoding to select the 1/2/4/8 byte elemsize for an Arm64 Sve vector instruction
7444+
* Returns the encoding to select the 1/2/4 byte elemsize for an Arm64 Sve narrowing vector instruction
74457445
*/
74467446

74477447
/*static*/ emitter::code_t emitter::insEncodeNarrowingSveElemsize(emitAttr size)

‎src/coreclr/jit/hwintrinsicarm64.cpp‎

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3405,6 +3405,27 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
34053405
break;
34063406
}
34073407

3408+
case NI_Sve2_SubtractWideningEven:
3409+
case NI_Sve2_SubtractWideningOdd:
3410+
{
3411+
assert(sig->numArgs == 2);
3412+
3413+
CORINFO_ARG_LIST_HANDLE arg1 = sig->args;
3414+
CORINFO_ARG_LIST_HANDLE arg2 = info.compCompHnd->getArgNext(arg1);
3415+
CORINFO_CLASS_HANDLE argClass = NO_CLASS_HANDLE;
3416+
3417+
JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg2, &argClass)));
3418+
JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg1, &argClass)));
3419+
op2 = impPopStack().val;
3420+
op1 = impPopStack().val;
3421+
3422+
CorInfoType op1BaseJitType = getBaseJitTypeOfSIMDType(argClass);
3423+
retNode = gtNewSimdHWIntrinsicNode(retType, op1, op2, intrinsic, simdBaseJitType, simdSize);
3424+
retNode->AsHWIntrinsic()->SetSimdBaseJitType(simdBaseJitType);
3425+
retNode->AsHWIntrinsic()->SetAuxiliaryJitType(op1BaseJitType);
3426+
break;
3427+
}
3428+
34083429
default:
34093430
{
34103431
return nullptr;

‎src/coreclr/jit/hwintrinsiccodegenarm64.cpp‎

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2744,6 +2744,30 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
27442744
GetEmitter()->emitInsSve_R_R_R(ins, emitSize, targetReg, op3Reg, op1Reg, INS_OPTS_SCALABLE_D);
27452745
break;
27462746

2747+
case NI_Sve2_SubtractWideningEven:
2748+
{
2749+
var_types returnType = node->AsHWIntrinsic()->GetSimdBaseType();
2750+
var_types op1Type = node->AsHWIntrinsic()->GetAuxiliaryType();
2751+
if (returnType != op1Type)
2752+
{
2753+
ins = varTypeIsUnsigned(intrin.baseType) ? INS_sve_usublb : INS_sve_ssublb;
2754+
}
2755+
GetEmitter()->emitInsSve_R_R_R(ins, emitSize, targetReg, op1Reg, op2Reg, opt);
2756+
break;
2757+
}
2758+
2759+
case NI_Sve2_SubtractWideningOdd:
2760+
{
2761+
var_types returnType = node->AsHWIntrinsic()->GetSimdBaseType();
2762+
var_types op1Type = node->AsHWIntrinsic()->GetAuxiliaryType();
2763+
if (returnType != op1Type)
2764+
{
2765+
ins = varTypeIsUnsigned(intrin.baseType) ? INS_sve_usublt : INS_sve_ssublt;
2766+
}
2767+
GetEmitter()->emitInsSve_R_R_R(ins, emitSize, targetReg, op1Reg, op2Reg, opt);
2768+
break;
2769+
}
2770+
27472771
default:
27482772
unreached();
27492773
}

‎src/coreclr/jit/hwintrinsiclistarm64sve.h‎

Lines changed: 12 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -370,8 +370,18 @@ HARDWARE_INTRINSIC(Sve2, ShiftRightLogicalRoundedNarrowingEven,
370370
HARDWARE_INTRINSIC(Sve2, ShiftRightLogicalRoundedNarrowingOdd, -1, 3, {INS_sve_rshrnt, INS_sve_rshrnt, INS_sve_rshrnt, INS_sve_rshrnt, INS_sve_rshrnt, INS_sve_rshrnt, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_ShiftRightByImmediate, HW_Flag_Scalable|HW_Flag_HasImmediateOperand|HW_Flag_HasRMWSemantics)
371371
HARDWARE_INTRINSIC(Sve2, ShiftRightLogicalRoundedNarrowingSaturateEven, -1, 2, {INS_invalid, INS_sve_uqrshrnb, INS_invalid, INS_sve_uqrshrnb, INS_invalid, INS_sve_uqrshrnb, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_ShiftRightByImmediate, HW_Flag_Scalable|HW_Flag_HasImmediateOperand)
372372
HARDWARE_INTRINSIC(Sve2, ShiftRightLogicalRoundedNarrowingSaturateOdd, -1, 3, {INS_invalid, INS_sve_uqrshrnt, INS_invalid, INS_sve_uqrshrnt, INS_invalid, INS_sve_uqrshrnt, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_ShiftRightByImmediate, HW_Flag_Scalable|HW_Flag_HasImmediateOperand|HW_Flag_HasRMWSemantics)
373-
HARDWARE_INTRINSIC(Sve2, VectorTableLookup, -1, 2, {INS_sve_tbl, INS_sve_tbl, INS_sve_tbl, INS_sve_tbl, INS_sve_tbl, INS_sve_tbl, INS_sve_tbl, INS_sve_tbl, INS_sve_tbl, INS_sve_tbl}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_NeedsConsecutiveRegisters|HW_Flag_SpecialImport|HW_Flag_SpecialCodeGen)
374-
HARDWARE_INTRINSIC(Sve2, VectorTableLookupExtension, -1, 3, {INS_sve_tbx, INS_sve_tbx, INS_sve_tbx, INS_sve_tbx, INS_sve_tbx, INS_sve_tbx, INS_sve_tbx, INS_sve_tbx, INS_sve_tbx, INS_sve_tbx}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_HasRMWSemantics)
373+
HARDWARE_INTRINSIC(Sve2, SubtractHighNarrowingEven, -1, 2, {INS_sve_subhnb, INS_sve_subhnb, INS_sve_subhnb, INS_sve_subhnb, INS_sve_subhnb, INS_sve_subhnb, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable)
374+
HARDWARE_INTRINSIC(Sve2, SubtractHighNarrowingOdd, -1, 3, {INS_sve_subhnt, INS_sve_subhnt, INS_sve_subhnt, INS_sve_subhnt, INS_sve_subhnt, INS_sve_subhnt, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_HasRMWSemantics)
375+
HARDWARE_INTRINSIC(Sve2, SubtractSaturate, -1, -1, {INS_sve_sqsub, INS_sve_uqsub, INS_sve_sqsub, INS_sve_uqsub, INS_sve_sqsub, INS_sve_uqsub, INS_sve_sqsub, INS_sve_uqsub, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_HasRMWSemantics)
376+
HARDWARE_INTRINSIC(Sve2, SubtractSaturateReversed, -1, -1, {INS_sve_sqsubr, INS_sve_uqsubr, INS_sve_sqsubr, INS_sve_uqsubr, INS_sve_sqsubr, INS_sve_uqsubr, INS_sve_sqsubr, INS_sve_uqsubr, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_HasRMWSemantics)
377+
HARDWARE_INTRINSIC(Sve2, SubtractWideningEven, -1, 2, {INS_invalid, INS_invalid, INS_sve_ssubwb, INS_sve_usubwb, INS_sve_ssubwb, INS_sve_usubwb, INS_sve_ssubwb, INS_sve_usubwb, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_SpecialImport|HW_Flag_SpecialCodeGen)
378+
HARDWARE_INTRINSIC(Sve2, SubtractWideningEvenOdd, -1, 2, {INS_invalid, INS_invalid, INS_sve_ssublbt, INS_invalid, INS_sve_ssublbt, INS_invalid, INS_sve_ssublbt, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable)
379+
HARDWARE_INTRINSIC(Sve2, SubtractWideningOdd, -1, 2, {INS_invalid, INS_invalid, INS_sve_ssubwt, INS_sve_usubwt, INS_sve_ssubwt, INS_sve_usubwt, INS_sve_ssubwt, INS_sve_usubwt, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_SpecialImport|HW_Flag_SpecialCodeGen)
380+
HARDWARE_INTRINSIC(Sve2, SubtractWideningOddEven, -1, 2, {INS_invalid, INS_invalid, INS_sve_ssubltb, INS_invalid, INS_sve_ssubltb, INS_invalid, INS_sve_ssubltb, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable)
381+
HARDWARE_INTRINSIC(Sve2, SubtractWithBorrowWideningLower, -1, 3, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_sbclb, INS_invalid, INS_sve_sbclb, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_HasRMWSemantics)
382+
HARDWARE_INTRINSIC(Sve2, SubtractWithBorrowWideningUpper, -1, 3, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_sbclt, INS_invalid, INS_sve_sbclt, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_HasRMWSemantics)
383+
HARDWARE_INTRINSIC(Sve2, VectorTableLookup, -1, 2, {INS_sve_tbl, INS_sve_tbl, INS_sve_tbl, INS_sve_tbl, INS_sve_tbl, INS_sve_tbl, INS_sve_tbl, INS_sve_tbl, INS_sve_tbl, INS_sve_tbl}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_NeedsConsecutiveRegisters|HW_Flag_SpecialImport|HW_Flag_SpecialCodeGen)
384+
HARDWARE_INTRINSIC(Sve2, VectorTableLookupExtension, -1, 3, {INS_sve_tbx, INS_sve_tbx, INS_sve_tbx, INS_sve_tbx, INS_sve_tbx, INS_sve_tbx, INS_sve_tbx, INS_sve_tbx, INS_sve_tbx, INS_sve_tbx}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_HasRMWSemantics)
375385
HARDWARE_INTRINSIC(Sve2, Xor, -1, 3, {INS_sve_eor3, INS_sve_eor3, INS_sve_eor3, INS_sve_eor3, INS_sve_eor3, INS_sve_eor3, INS_sve_eor3, INS_sve_eor3, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_HasRMWSemantics)
376386
HARDWARE_INTRINSIC(Sve2, XorRotateRight, -1, 3, {INS_sve_xar, INS_sve_xar, INS_sve_xar, INS_sve_xar, INS_sve_xar, INS_sve_xar, INS_sve_xar, INS_sve_xar, INS_invalid, INS_invalid}, HW_Category_ShiftRightByImmediate, HW_Flag_Scalable|HW_Flag_HasRMWSemantics|HW_Flag_HasImmediateOperand)
377387
#define LAST_NI_Sve2 NI_Sve2_XorRotateRight

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