Skip to content

Commit 9fd71bb

Browse files
authored
Merge pull request #2444 from hzeller/feature-20250813-update-smoke-expectations
Update smoke-test expectations.
2 parents ba3dc37 + 72b965d commit 9fd71bb

File tree

1 file changed

+15
-15
lines changed

1 file changed

+15
-15
lines changed

.github/bin/smoke-test.sh

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -135,24 +135,24 @@ declare -A ExpectedFailCount
135135

136136
ExpectedFailCount[syntax:ibex]=17
137137
ExpectedFailCount[lint:ibex]=17
138-
ExpectedFailCount[project:ibex]=220
138+
ExpectedFailCount[project:ibex]=222
139139
ExpectedFailCount[preprocessor:ibex]=394
140140

141-
ExpectedFailCount[syntax:opentitan]=99
142-
ExpectedFailCount[lint:opentitan]=99
143-
ExpectedFailCount[project:opentitan]=1137
141+
ExpectedFailCount[syntax:opentitan]=101
142+
ExpectedFailCount[lint:opentitan]=101
143+
ExpectedFailCount[project:opentitan]=1133
144144
ExpectedFailCount[formatter:opentitan]=0
145-
ExpectedFailCount[preprocessor:opentitan]=3057
145+
ExpectedFailCount[preprocessor:opentitan]=3061
146146

147147
ExpectedFailCount[syntax:sv-tests]=77
148148
ExpectedFailCount[lint:sv-tests]=76
149149
ExpectedFailCount[project:sv-tests]=187
150150
ExpectedFailCount[preprocessor:sv-tests]=139
151151

152-
ExpectedFailCount[syntax:caliptra-rtl]=27
153-
ExpectedFailCount[lint:caliptra-rtl]=26
154-
ExpectedFailCount[project:caliptra-rtl]=413
155-
ExpectedFailCount[preprocessor:caliptra-rtl]=872
152+
ExpectedFailCount[syntax:caliptra-rtl]=39
153+
ExpectedFailCount[lint:caliptra-rtl]=38
154+
ExpectedFailCount[project:caliptra-rtl]=419
155+
ExpectedFailCount[preprocessor:caliptra-rtl]=879
156156

157157
ExpectedFailCount[syntax:Cores-VeeR-EH2]=2
158158
ExpectedFailCount[lint:Cores-VeeR-EH2]=2
@@ -197,8 +197,8 @@ ExpectedFailCount[lint:nontrivial-mips]=2
197197
ExpectedFailCount[project:nontrivial-mips]=81
198198
ExpectedFailCount[preprocessor:nontrivial-mips]=78
199199

200-
ExpectedFailCount[project:axi]=78
201-
ExpectedFailCount[preprocessor:axi]=75
200+
ExpectedFailCount[project:axi]=80
201+
ExpectedFailCount[preprocessor:axi]=77
202202

203203
ExpectedFailCount[syntax:rsd]=5
204204
ExpectedFailCount[lint:rsd]=5
@@ -211,11 +211,11 @@ ExpectedFailCount[preprocessor:scr1]=46
211211
ExpectedFailCount[project:serv]=1
212212
ExpectedFailCount[preprocessor:serv]=1
213213

214-
ExpectedFailCount[syntax:basejump_stl]=487
215-
ExpectedFailCount[lint:basejump_stl]=487
216-
ExpectedFailCount[project:basejump_stl]=604
214+
ExpectedFailCount[syntax:basejump_stl]=490
215+
ExpectedFailCount[lint:basejump_stl]=490
216+
ExpectedFailCount[project:basejump_stl]=609
217217
ExpectedFailCount[formatter:basejump_stl]=1
218-
ExpectedFailCount[preprocessor:basejump_stl]=643
218+
ExpectedFailCount[preprocessor:basejump_stl]=648
219219

220220
ExpectedFailCount[syntax:opl3_fpga]=3
221221
ExpectedFailCount[lint:opl3_fpga]=3

0 commit comments

Comments
 (0)