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@yrabbit yrabbit commented Dec 20, 2022

Corrects a mistake where non-existent wires were created for chips with 4 quadrants.

Fix #143

Signed-off-by: YRabbit [email protected]

Corrects a mistake where non-existent wires were created for chips with 4 quadrants.

Signed-off-by: YRabbit <[email protected]>
@pepijndevos pepijndevos merged commit 20af410 into YosysHQ:master Dec 20, 2022
@yrabbit yrabbit deleted the clock-aliases branch April 18, 2023 22:38
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Stopped triggering on posedge clk/52 in the 2022-12-16 release

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