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Copy file name to clipboardExpand all lines: doc/longwires.md
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@@ -176,35 +176,38 @@ For type 12:
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| CE2 132 | X | X | X | X |||| X |
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# E
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The two cells in the center of the chip with types 81 and 82 are responsible for sources for long wires.
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The two cells in the center of the chip with types 81 and 82 are responsible for sources for long wires. Here I also add two adjacent cells with types 83 and 84. 83 contains 7 muxes for lines 40--46 and 84 contains a mux for line 47.
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These lines 40--47 are connected to buses `SS00` and `SS40` in the bottom row of the chip. But so far I can't get the vendor IDE to use them so their purpose is unclear.
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The `+` marked sources whose locations are known and I will explain how to find them.
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The `dat` dictionary has a table `UfbIns`, whose entries have the structure `[row number, column number, pip code]`. Thus the entry `[4, 1, 126]` means that CLK2 pip in cell [4, 1] is an entry point to somewhere.
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Experimentally it is found that CLK2 are the entry points to the long wire system and it is these points that are marked with a `+` sign in the table above.
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