Skip to content

Commit d655766

Browse files
committed
Smallfix
1 parent 89f9035 commit d655766

File tree

1 file changed

+8
-7
lines changed

1 file changed

+8
-7
lines changed

frontends/verific/verific.cc

Lines changed: 8 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -3736,14 +3736,15 @@ struct VerificPass : public Pass {
37363736
veri_file::DefineMacro(is_formal ? "FORMAL" : "SYNTHESIS");
37373737
*/
37383738

3739-
// SILIMATE: VHDL processing
3739+
// SILIMATE: VHDL processing using GHDL
37403740
int i;
37413741
FOREACH_ARRAY_ITEM(file_names, i, filename) {
3742-
std::string file_name_str = filename;
3742+
// Convert filename to std::string
3743+
std::string filename_str = filename;
37433744

37443745
// Check if file is VHDL
3745-
if (file_name_str.substr(file_name_str.find_last_of(".") + 1) == "vhd") goto is_vhdl;
3746-
if (file_name_str.substr(file_name_str.find_last_of(".") + 1) == "vhdl") goto is_vhdl;
3746+
if (filename_str.substr(filename_str.find_last_of(".") + 1) == "vhd") goto is_vhdl;
3747+
if (filename_str.substr(filename_str.find_last_of(".") + 1) == "vhdl") goto is_vhdl;
37473748
continue;
37483749

37493750
// Convert to Verilog
@@ -3763,17 +3764,17 @@ struct VerificPass : public Pass {
37633764
if (!FileSystem::PathExists(ghdl_path.c_str())) ghdl_path = "ghdl";
37643765

37653766
// Run command to convert VHDL to Verilog
3766-
std::string top = file_name_str.substr(0, std::string(FileSystem::Basename(filename)).find_last_of("."));
3767+
std::string top = filename_str.substr(0, std::string(FileSystem::Basename(filename)).find_last_of("."));
37673768
std::string outfile = "preqorsor/data/" + top + ".v";
3768-
std::string ghdl_cmd = ghdl_path + " --synth --no-formal --out=verilog " + file_name_str + " -e " + top + " > " + outfile;
3769+
std::string ghdl_cmd = ghdl_path + " --synth --no-formal --out=verilog " + filename_str + " -e " + top + " > " + outfile;
37693770
log("Running command: %s\n", ghdl_cmd.c_str());
37703771
if (system(ghdl_cmd.c_str()) != 0) {
37713772
verific_error_msg.clear();
37723773
log_cmd_error("Could not convert VHDL file %s to Verilog.\n", filename);
37733774
}
37743775

37753776
// Add file
3776-
file_names->Insert(i, outfile.c_str());
3777+
file_names->Insert(i, Strings::save(outfile.c_str()));
37773778
}
37783779

37793780
if (!veri_file::AnalyzeMultipleFiles(file_names, analysis_mode, work.c_str(), veri_file::MFCU)) {

0 commit comments

Comments
 (0)