@@ -3736,14 +3736,15 @@ struct VerificPass : public Pass {
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veri_file::DefineMacro(is_formal ? "FORMAL" : "SYNTHESIS");
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*/
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- // SILIMATE: VHDL processing
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+ // SILIMATE: VHDL processing using GHDL
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int i;
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FOREACH_ARRAY_ITEM (file_names, i, filename) {
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- std::string file_name_str = filename;
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+ // Convert filename to std::string
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+ std::string filename_str = filename;
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// Check if file is VHDL
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- if (file_name_str .substr (file_name_str .find_last_of (" ." ) + 1 ) == " vhd" ) goto is_vhdl;
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- if (file_name_str .substr (file_name_str .find_last_of (" ." ) + 1 ) == " vhdl" ) goto is_vhdl;
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+ if (filename_str .substr (filename_str .find_last_of (" ." ) + 1 ) == " vhd" ) goto is_vhdl;
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+ if (filename_str .substr (filename_str .find_last_of (" ." ) + 1 ) == " vhdl" ) goto is_vhdl;
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continue ;
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// Convert to Verilog
@@ -3763,17 +3764,17 @@ struct VerificPass : public Pass {
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if (!FileSystem::PathExists (ghdl_path.c_str ())) ghdl_path = " ghdl" ;
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// Run command to convert VHDL to Verilog
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- std::string top = file_name_str .substr (0 , std::string (FileSystem::Basename (filename)).find_last_of (" ." ));
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+ std::string top = filename_str .substr (0 , std::string (FileSystem::Basename (filename)).find_last_of (" ." ));
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std::string outfile = " preqorsor/data/" + top + " .v" ;
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- std::string ghdl_cmd = ghdl_path + " --synth --no-formal --out=verilog " + file_name_str + " -e " + top + " > " + outfile;
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+ std::string ghdl_cmd = ghdl_path + " --synth --no-formal --out=verilog " + filename_str + " -e " + top + " > " + outfile;
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log (" Running command: %s\n " , ghdl_cmd.c_str ());
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if (system (ghdl_cmd.c_str ()) != 0 ) {
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verific_error_msg.clear ();
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log_cmd_error (" Could not convert VHDL file %s to Verilog.\n " , filename);
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}
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// Add file
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- file_names->Insert (i, outfile.c_str ());
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+ file_names->Insert (i, Strings::save ( outfile.c_str () ));
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}
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if (!veri_file::AnalyzeMultipleFiles (file_names, analysis_mode, work.c_str (), veri_file::MFCU)) {
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