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airliedairlied
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Merge tag 'drm-fixes-5.3-2019-07-24' of git://people.freedesktop.org/~agd5f/linux into drm-fixes
drm-fixes-5.3-2019-07-24: amdgpu: - RAS fixes for vega20 - Navi VCN fix - DC audio fixes - DC DSC fixes - DC dongle fixes - DC clk mgr fixes - Fix DDC lines on some RV2 boards - GDS fixes for compute - Navi SMU fixes ttm: - Use the same attributes when freeing d_page->vaddr Signed-off-by: Dave Airlie <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2 parents f480de3 + 92e6475 commit 4d5308e

38 files changed

+437
-152
lines changed

‎drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -148,7 +148,7 @@ struct amdgpu_mgpu_info mgpu_info = {
148148
.mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
149149
};
150150
int amdgpu_ras_enable = -1;
151-
uint amdgpu_ras_mask = 0xffffffff;
151+
uint amdgpu_ras_mask = 0xfffffffb;
152152

153153
/**
154154
* DOC: vramlimit (int)

‎drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1734,7 +1734,7 @@ static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
17341734
return -EINVAL;
17351735

17361736
if (is_support_sw_smu(adev)) {
1737-
err = smu_get_current_rpm(&adev->smu, &speed);
1737+
err = smu_get_fan_speed_rpm(&adev->smu, &speed);
17381738
if (err)
17391739
return err;
17401740
} else if (adev->powerplay.pp_funcs->get_fan_speed_rpm) {
@@ -1794,7 +1794,7 @@ static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev,
17941794
return -EINVAL;
17951795

17961796
if (is_support_sw_smu(adev)) {
1797-
err = smu_get_current_rpm(&adev->smu, &rpm);
1797+
err = smu_get_fan_speed_rpm(&adev->smu, &rpm);
17981798
if (err)
17991799
return err;
18001800
} else if (adev->powerplay.pp_funcs->get_fan_speed_rpm) {

‎drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c‎

Lines changed: 12 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -136,11 +136,6 @@ static int amdgpu_ras_reserve_vram(struct amdgpu_device *adev,
136136
static int amdgpu_ras_release_vram(struct amdgpu_device *adev,
137137
struct amdgpu_bo **bo_ptr);
138138

139-
static void amdgpu_ras_self_test(struct amdgpu_device *adev)
140-
{
141-
/* TODO */
142-
}
143-
144139
static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf,
145140
size_t size, loff_t *pos)
146141
{
@@ -689,6 +684,12 @@ int amdgpu_ras_error_inject(struct amdgpu_device *adev,
689684
if (!obj)
690685
return -EINVAL;
691686

687+
if (block_info.block_id != TA_RAS_BLOCK__UMC) {
688+
DRM_INFO("%s error injection is not supported yet\n",
689+
ras_block_str(info->head.block));
690+
return -EINVAL;
691+
}
692+
692693
ret = psp_ras_trigger_error(&adev->psp, &block_info);
693694
if (ret)
694695
DRM_ERROR("RAS ERROR: inject %s error failed ret %d\n",
@@ -1557,6 +1558,12 @@ int amdgpu_ras_init(struct amdgpu_device *adev)
15571558

15581559
amdgpu_ras_check_supported(adev, &con->hw_supported,
15591560
&con->supported);
1561+
if (!con->hw_supported) {
1562+
amdgpu_ras_set_context(adev, NULL);
1563+
kfree(con);
1564+
return 0;
1565+
}
1566+
15601567
con->features = 0;
15611568
INIT_LIST_HEAD(&con->head);
15621569
/* Might need get this flag from vbios. */
@@ -1570,8 +1577,6 @@ int amdgpu_ras_init(struct amdgpu_device *adev)
15701577
if (amdgpu_ras_fs_init(adev))
15711578
goto fs_out;
15721579

1573-
amdgpu_ras_self_test(adev);
1574-
15751580
DRM_INFO("RAS INFO: ras initialized successfully, "
15761581
"hardware ability[%x] ras_mask[%x]\n",
15771582
con->hw_supported, con->supported);

‎drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1441,6 +1441,15 @@ static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
14411441
}
14421442
nv_grbm_select(adev, 0, 0, 0, 0);
14431443
mutex_unlock(&adev->srbm_mutex);
1444+
1445+
/* Initialize all compute VMIDs to have no GDS, GWS, or OA
1446+
acccess. These should be enabled by FW for target VMIDs. */
1447+
for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1448+
WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
1449+
WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
1450+
WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
1451+
WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
1452+
}
14441453
}
14451454

14461455
static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)

‎drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1879,6 +1879,15 @@ static void gfx_v7_0_init_compute_vmid(struct amdgpu_device *adev)
18791879
}
18801880
cik_srbm_select(adev, 0, 0, 0, 0);
18811881
mutex_unlock(&adev->srbm_mutex);
1882+
1883+
/* Initialize all compute VMIDs to have no GDS, GWS, or OA
1884+
acccess. These should be enabled by FW for target VMIDs. */
1885+
for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1886+
WREG32(amdgpu_gds_reg_offset[i].mem_base, 0);
1887+
WREG32(amdgpu_gds_reg_offset[i].mem_size, 0);
1888+
WREG32(amdgpu_gds_reg_offset[i].gws, 0);
1889+
WREG32(amdgpu_gds_reg_offset[i].oa, 0);
1890+
}
18821891
}
18831892

18841893
static void gfx_v7_0_config_init(struct amdgpu_device *adev)

‎drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3706,6 +3706,15 @@ static void gfx_v8_0_init_compute_vmid(struct amdgpu_device *adev)
37063706
}
37073707
vi_srbm_select(adev, 0, 0, 0, 0);
37083708
mutex_unlock(&adev->srbm_mutex);
3709+
3710+
/* Initialize all compute VMIDs to have no GDS, GWS, or OA
3711+
acccess. These should be enabled by FW for target VMIDs. */
3712+
for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
3713+
WREG32(amdgpu_gds_reg_offset[i].mem_base, 0);
3714+
WREG32(amdgpu_gds_reg_offset[i].mem_size, 0);
3715+
WREG32(amdgpu_gds_reg_offset[i].gws, 0);
3716+
WREG32(amdgpu_gds_reg_offset[i].oa, 0);
3717+
}
37093718
}
37103719

37113720
static void gfx_v8_0_config_init(struct amdgpu_device *adev)

‎drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1918,6 +1918,15 @@ static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
19181918
}
19191919
soc15_grbm_select(adev, 0, 0, 0, 0);
19201920
mutex_unlock(&adev->srbm_mutex);
1921+
1922+
/* Initialize all compute VMIDs to have no GDS, GWS, or OA
1923+
acccess. These should be enabled by FW for target VMIDs. */
1924+
for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1925+
WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
1926+
WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
1927+
WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
1928+
WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
1929+
}
19211930
}
19221931

19231932
static void gfx_v9_0_constants_init(struct amdgpu_device *adev)

‎drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c‎

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -372,11 +372,8 @@ static void vcn_v2_0_mc_resume(struct amdgpu_device *adev)
372372
WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
373373
upper_32_bits(adev->vcn.gpu_addr));
374374
offset = size;
375-
/* No signed header for now from firmware
376375
WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
377376
AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
378-
*/
379-
WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0);
380377
}
381378

382379
WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);

‎drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -262,12 +262,12 @@ void dce110_clk_mgr_construct(
262262
struct dc_context *ctx,
263263
struct clk_mgr_internal *clk_mgr)
264264
{
265+
dce_clk_mgr_construct(ctx, clk_mgr);
266+
265267
memcpy(clk_mgr->max_clks_by_state,
266268
dce110_max_clks_by_state,
267269
sizeof(dce110_max_clks_by_state));
268270

269-
dce_clk_mgr_construct(ctx, clk_mgr);
270-
271271
clk_mgr->regs = &disp_clk_regs;
272272
clk_mgr->clk_mgr_shift = &disp_clk_shift;
273273
clk_mgr->clk_mgr_mask = &disp_clk_mask;

‎drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -226,12 +226,12 @@ void dce112_clk_mgr_construct(
226226
struct dc_context *ctx,
227227
struct clk_mgr_internal *clk_mgr)
228228
{
229+
dce_clk_mgr_construct(ctx, clk_mgr);
230+
229231
memcpy(clk_mgr->max_clks_by_state,
230232
dce112_max_clks_by_state,
231233
sizeof(dce112_max_clks_by_state));
232234

233-
dce_clk_mgr_construct(ctx, clk_mgr);
234-
235235
clk_mgr->regs = &disp_clk_regs;
236236
clk_mgr->clk_mgr_shift = &disp_clk_shift;
237237
clk_mgr->clk_mgr_mask = &disp_clk_mask;

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