@@ -8863,6 +8863,13 @@ const struct flashchip flashchips[] = {
8863
8863
.write = spi_chip_write_256,
8864
8864
.read = spi_chip_read, /* Fast read (0x0B) and dual I/O supported */
8865
8865
.voltage = {2700, 3600},
8866
+ .reg_bits =
8867
+ {
8868
+ .srp = {STATUS1, 7, RW},
8869
+ .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}},
8870
+ .cmp = {STATUS1, 5, RW}, /* Called BP3 in datasheet, acts like CMP */
8871
+ },
8872
+ .decode_range = decode_range_spi25_bit_cmp,
8866
8873
},
8867
8874
8868
8875
{
@@ -9089,6 +9096,12 @@ const struct flashchip flashchips[] = {
9089
9096
.write = spi_chip_write_256,
9090
9097
.read = spi_chip_read, /* Fast read (0x0B) supported */
9091
9098
.voltage = {2700, 3600},
9099
+ .reg_bits =
9100
+ {
9101
+ .srp = {STATUS1, 7, RW},
9102
+ .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}},
9103
+ },
9104
+ .decode_range = decode_range_spi25,
9092
9105
},
9093
9106
9094
9107
{
@@ -9125,6 +9138,13 @@ const struct flashchip flashchips[] = {
9125
9138
.write = spi_chip_write_256,
9126
9139
.read = spi_chip_read, /* Fast read (0x0B), dual I/O read (0xBB) supported */
9127
9140
.voltage = {2700, 3600},
9141
+ .reg_bits =
9142
+ {
9143
+ .srp = {STATUS1, 7, RW},
9144
+ .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}},
9145
+ .cmp = {STATUS1, 5, RW}, /* Called BP3 in datasheet, acts like CMP */
9146
+ },
9147
+ .decode_range = decode_range_spi25_bit_cmp,
9128
9148
},
9129
9149
9130
9150
{
@@ -9165,19 +9185,26 @@ const struct flashchip flashchips[] = {
9165
9185
.write = spi_chip_write_256,
9166
9186
.read = spi_chip_read, /* Fast read (0x0B), dual I/O read supported */
9167
9187
.voltage = {2700, 3600},
9188
+ .reg_bits =
9189
+ {
9190
+ .srp = {STATUS1, 7, RW},
9191
+ .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}},
9192
+ .cmp = {STATUS1, 5, RW}, /* Called BP3 in datasheet, acts like CMP */
9193
+ },
9194
+ .decode_range = decode_range_spi25_bit_cmp,
9168
9195
},
9169
9196
9170
9197
{
9171
9198
.vendor = "Macronix",
9172
- .name = "MX25L6436E/MX25L6445E/MX25L6465E/MX25L6473E/MX25L6473F ",
9199
+ .name = "MX25L6436E/MX25L6445E/MX25L6465E",
9173
9200
.bustype = BUS_SPI,
9174
9201
.manufacture_id = MACRONIX_ID,
9175
9202
.model_id = MACRONIX_MX25L6405,
9176
9203
.total_size = 8192,
9177
9204
.page_size = 256,
9178
9205
/* supports SFDP */
9179
9206
/* OTP: 512B total; enter 0xB1, exit 0xC1 */
9180
- .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP,
9207
+ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_SCUR ,
9181
9208
.tested = TEST_OK_PREW,
9182
9209
.probe = probe_spi_rdid,
9183
9210
.probe_timing = TIMING_ZERO,
@@ -9205,6 +9232,108 @@ const struct flashchip flashchips[] = {
9205
9232
.write = spi_chip_write_256,
9206
9233
.read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */
9207
9234
.voltage = {2700, 3600},
9235
+ .reg_bits =
9236
+ {
9237
+ .srp = {STATUS1, 7, RW},
9238
+ .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}},
9239
+ .wps = {SECREG, 7, OTP}, /* This bit is set by WPSEL command */
9240
+ },
9241
+ .decode_range = decode_range_spi25_2x_block,
9242
+ },
9243
+
9244
+ {
9245
+ .vendor = "Macronix",
9246
+ .name = "MX25L6473E",
9247
+ .bustype = BUS_SPI,
9248
+ .manufacture_id = MACRONIX_ID,
9249
+ .model_id = MACRONIX_MX25L6405,
9250
+ .total_size = 8192,
9251
+ .page_size = 256,
9252
+ /* supports SFDP */
9253
+ /* OTP: 512B total; enter 0xB1, exit 0xC1 */
9254
+ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_WRSR_EXT2 | FEATURE_SCUR | FEATURE_CR,
9255
+ .tested = TEST_OK_PREW,
9256
+ .probe = probe_spi_rdid,
9257
+ .probe_timing = TIMING_ZERO,
9258
+ .block_erasers =
9259
+ {
9260
+ {
9261
+ .eraseblocks = { {4 * 1024, 2048} },
9262
+ .block_erase = spi_block_erase_20,
9263
+ }, {
9264
+ .eraseblocks = { {32 * 1024, 256} },
9265
+ .block_erase = spi_block_erase_52,
9266
+ }, {
9267
+ .eraseblocks = { {64 * 1024, 128} },
9268
+ .block_erase = spi_block_erase_d8,
9269
+ }, {
9270
+ .eraseblocks = { {8 * 1024 * 1024, 1} },
9271
+ .block_erase = spi_block_erase_60,
9272
+ }, {
9273
+ .eraseblocks = { {8 * 1024 * 1024, 1} },
9274
+ .block_erase = spi_block_erase_c7,
9275
+ }
9276
+ },
9277
+ .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */
9278
+ .unlock = spi_disable_blockprotect_bp3_srwd,
9279
+ .write = spi_chip_write_256,
9280
+ .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */
9281
+ .voltage = {2700, 3600},
9282
+ .reg_bits =
9283
+ {
9284
+ .srp = {STATUS1, 7, RW},
9285
+ .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}},
9286
+ .tb = {CFGREG, 3, OTP},
9287
+ .wps = {SECREG, 7, OTP}, /* This bit is set by WPSEL command */
9288
+ },
9289
+ .decode_range = decode_range_spi25,
9290
+ },
9291
+
9292
+ {
9293
+ .vendor = "Macronix",
9294
+ .name = "MX25L6473F",
9295
+ .bustype = BUS_SPI,
9296
+ .manufacture_id = MACRONIX_ID,
9297
+ .model_id = MACRONIX_MX25L6405,
9298
+ .total_size = 8192,
9299
+ .page_size = 256,
9300
+ /* supports SFDP */
9301
+ /* OTP: 512B total; enter 0xB1, exit 0xC1 */
9302
+ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_WRSR_EXT2 | FEATURE_CR,
9303
+ .tested = TEST_OK_PREW,
9304
+ .probe = probe_spi_rdid,
9305
+ .probe_timing = TIMING_ZERO,
9306
+ .block_erasers =
9307
+ {
9308
+ {
9309
+ .eraseblocks = { {4 * 1024, 2048} },
9310
+ .block_erase = spi_block_erase_20,
9311
+ }, {
9312
+ .eraseblocks = { {32 * 1024, 256} },
9313
+ .block_erase = spi_block_erase_52,
9314
+ }, {
9315
+ .eraseblocks = { {64 * 1024, 128} },
9316
+ .block_erase = spi_block_erase_d8,
9317
+ }, {
9318
+ .eraseblocks = { {8 * 1024 * 1024, 1} },
9319
+ .block_erase = spi_block_erase_60,
9320
+ }, {
9321
+ .eraseblocks = { {8 * 1024 * 1024, 1} },
9322
+ .block_erase = spi_block_erase_c7,
9323
+ }
9324
+ },
9325
+ .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */
9326
+ .unlock = spi_disable_blockprotect_bp3_srwd,
9327
+ .write = spi_chip_write_256,
9328
+ .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */
9329
+ .voltage = {2700, 3600},
9330
+ .reg_bits =
9331
+ {
9332
+ .srp = {STATUS1, 7, RW},
9333
+ .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}},
9334
+ .tb = {CFGREG, 3, OTP},
9335
+ },
9336
+ .decode_range = decode_range_spi25,
9208
9337
},
9209
9338
9210
9339
{
0 commit comments