Fiting logical operations into LUT4

[jeras]

The first commit:

• white-space fixes,
• Verilog 2001 style parameter definition.

Second commit attempts to fit all logical operations into a single LUT4 array.
LUT4 has 4 inputs op1, op2 and func3[1:0] and can implement all logical operations with one to spare.

After running make ICESTICK, I noticed a 15 LC reduction in logic utilization (~4%).
My assumption is a LUT4 was used for logical operations instead of multiplexing 3 separate calculations.
I did not look into reports or the netlist to check for details.

I did run a regression test to see if I introduced any bugs, and it seems to work.

[jeras]

The third commit, attempts to replace some one-hot multiplexers with binary select multiplexers.

One hot multiplexers do not have an obvious advantage over binary select.
The synthesis tool might optimize a multiplexer regardless if the select signal was converted from binary to one-hot.

Both the ALU func3 and BRANCH func3 multiplexers have been modified.

The ALU change does not provide a LC consumption change, this might mean, the synthesis too ignored the initial conversion from binary to one-hot.

The BRANCH predicate code reduces the LC usage by 2. This is not much, but a large change could not be expected since the entire multiplexer only has 3 select bits (func3) and 3 single bit values (EQ/LT/LTU and their inverts) to multiplex to a single bit output. The 2 LC reduction might have come from the use of don't care values (1'bx).

[jeras]

Commit 4 is again cosmetic.

Commit 5 changes the store data encoder, the change reduced the LC count by 2.

Commit 6 fixes the issue with load/store alignment tests.
Most systems with a 32bit data bus do not use addr[1:0], so this two bits are usually fixed.
My test environment uses those two bits to allow for unaligned access tests, therefore some alignment tests failed if those bits were not zero.
If the two LSB address bits are not used anywhere in the SoC then it makes sense to apply this patch.